Searched refs:nlm_read_nae_reg (Results 1 - 7 of 7) sorted by relevance

/freebsd-12-stable/sys/mips/nlm/hal/
H A Ducore_loader.h70 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
88 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
112 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
118 ucore_cfg = nlm_read_nae_reg(nae_base,
131 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
H A Dnae.h483 #define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r) macro
/freebsd-12-stable/sys/mips/nlm/dev/net/
H A Dmdio.c63 mdio_ld_cmd = nlm_read_nae_reg(nae_base,
81 while(nlm_read_nae_reg(nae_base,
91 return nlm_read_nae_reg(nae_base,
113 mdio_ld_cmd = nlm_read_nae_reg(nae_base,
135 while(nlm_read_nae_reg(nae_base,
186 mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
192 while(nlm_read_nae_reg(nae_base,
215 while(nlm_read_nae_reg(nae_base,
224 return nlm_read_nae_reg(nae_base,
247 mdio_ld_cmd = nlm_read_nae_reg(nae_bas
[all...]
H A Dxaui.c66 lane_enable = nlm_read_nae_reg(nae_base,
82 lane_enable = nlm_read_nae_reg(nae_base,
124 regval = nlm_read_nae_reg(nae_base, reg);
129 regval = nlm_read_nae_reg(nae_base, reg);
134 regval = nlm_read_nae_reg(nae_base, reg);
205 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
209 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
227 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
247 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
H A Dsgmii.c83 mac_cfg1 = nlm_read_nae_reg(nae_base,
85 mac_cfg2 = nlm_read_nae_reg(nae_base,
87 netwk_inf = nlm_read_nae_reg(nae_base,
158 val = nlm_read_nae_reg(base,
164 val = nlm_read_nae_reg(base,
H A Dnae.c57 data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP);
205 rx_config = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
392 val = nlm_read_nae_reg(nae_base,
411 saved_data = nlm_read_nae_reg(nae_base,
423 while (((val = nlm_read_nae_reg(nae_base,
451 while (!((val = nlm_read_nae_reg(nae_base,
456 val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl));
472 val = nlm_read_nae_reg(nae_base,
484 val = nlm_read_nae_reg(nae_base,
491 val = nlm_read_nae_reg(nae_bas
[all...]
H A Dxlpge.c265 value = nlm_read_nae_reg(sc->base, NAE_FREE_IN_FIFO_CFG);
292 data = nlm_read_nae_reg(sc->base, NAE_DMA_TX_CREDIT_TH);
418 val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
423 val = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
1147 val = nlm_read_nae_reg(sc->base_addr, reg);

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