1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003-2012 Broadcom Corporation
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in
15 *    the documentation and/or other materials provided with the
16 *    distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
25 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
26 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
27 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
28 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33#ifndef __NLM_UCORE_LOADER_H__
34#define	__NLM_UCORE_LOADER_H__
35
36/**
37* @file_name ucore_loader.h
38* @author Netlogic Microsystems
39* @brief Ucore loader API header
40*/
41
42#define	CODE_SIZE_PER_UCORE	(4 << 10)
43
44static __inline__ void
45nlm_ucore_load_image(uint64_t nae_base, int ucore)
46{
47	uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
48	    (ucore * CODE_SIZE_PER_UCORE);
49	uint32_t *p = (uint32_t *)ucore_app_bin;
50	int i, size;
51
52	size = sizeof(ucore_app_bin)/sizeof(uint32_t);
53	for (i = 0; i < size; i++, addr += 4)
54		nlm_store_word_daddr(addr, htobe32(p[i]));
55
56	/* add a 'nop' if number of instructions are odd */
57	if (size & 0x1)
58		nlm_store_word_daddr(addr, 0x0);
59}
60
61static __inline int
62nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
63{
64	uint32_t ucore_cfg;
65	uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
66
67	if (index > 128)
68		return (-1);
69
70	ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
71	/* set iram to zero */
72	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
73	    (ucore_cfg & ~(0x1 << 7)));
74
75	nlm_store_word_daddr(addr + (index * 4), data);
76
77	/* restore ucore config */
78	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
79	return (0);
80}
81
82static __inline uint32_t
83nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
84{
85	uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
86	uint32_t ucore_cfg, val;
87
88	ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
89	/* set iram to zero */
90	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
91	    (ucore_cfg & ~(0x1 << 7)));
92
93	val = nlm_load_word_daddr(addr + (index * 4));
94
95	/* restore ucore config */
96	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
97
98	return val;
99}
100
101static __inline__ int
102nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
103{
104	int i, count = 0;
105	uint32_t mask;
106	uint32_t ucore_cfg = 0;
107
108	mask = ucore_mask & 0xffff;
109
110	/* Stop all ucores */
111	if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
112		ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
113		nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
114		    ucore_cfg | (1 << 24));
115
116		/* poll for ucore to get in to a wait state */
117		do {
118			ucore_cfg = nlm_read_nae_reg(nae_base,
119			    NAE_RX_UCORE_CFG);
120		} while ((ucore_cfg & (1 << 25)) == 0);
121	}
122
123	for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
124		if ((mask & (1 << i)) == 0)
125			continue;
126		nlm_ucore_load_image(nae_base, i);
127		count++;
128	}
129
130	/* Enable per-domain ucores */
131	ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
132
133	/* write one to reset bits to put the ucores in reset */
134	ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
135	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
136
137	/* write zero to reset bits to pull them out of reset */
138	ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
139	nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
140
141	return (count);
142}
143#endif
144