Searched refs:lanes (Results 1 - 25 of 31) sorted by relevance

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/freebsd-12-stable/sys/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dargon2.c44 /* Minimum memory_blocks = 8L blocks, where L is the number of lanes */
47 if (memory_blocks < 2 * ARGON2_SYNC_POINTS * context->lanes) {
48 memory_blocks = 2 * ARGON2_SYNC_POINTS * context->lanes;
51 segment_length = memory_blocks / (context->lanes * ARGON2_SYNC_POINTS);
53 memory_blocks = segment_length * (context->lanes * ARGON2_SYNC_POINTS);
61 instance.lanes = context->lanes;
125 context.lanes = parallelism;
H A Dargon2-core.c197 for (l = 1; l < instance->lanes; ++l) {
227 if (instance == NULL || instance->lanes == 0) {
234 for (l = 0; l < instance->lanes; ++l) {
332 if (context->m_cost < 8 * context->lanes) {
345 /* Validate lanes */
346 if (ARGON2_MIN_LANES > context->lanes) {
350 if (ARGON2_MAX_LANES < context->lanes) {
374 for (l = 0; l < instance->lanes; ++l) {
404 STORE32_LE(value, context->lanes);
H A Dargon2-encoding.c186 DECIMAL_U32(ctx->lanes);
187 if (ctx->lanes > UINT32_MAX) {
190 ctx->threads = ctx->lanes;
293 SX(ctx->lanes);
H A Dargon2-core.h103 uint32_t lanes; member in struct:Argon2_instance_t
147 * Other lanes : all already finished segments
151 * Other lanes : (SYNC_POINTS - 1) last segments
H A Dargon2.h23 /* Minimum and maximum number of lanes (degree of parallelism) */
31 /* Number of synchronization points between lanes per pass */
156 *lanes.
181 uint32_t lanes; /* number of lanes */ member in struct:Argon2_Context
201 * @param parallelism Number of threads and compute lanes
222 * @param parallelism Number of threads and compute lanes
243 * @param parallelism Number of threads and compute lanes
262 * @param parallelism Number of threads and compute lanes
H A Dargon2-fill-block-avx2.c212 ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
215 /* Can not reference other lanes yet */
H A Dargon2-fill-block-avx512f.c217 ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
220 /* Can not reference other lanes yet */
H A Dargon2-fill-block-ref.c207 ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
210 /* Can not reference other lanes yet */
H A Dargon2-fill-block-ssse3.c211 ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
214 /* Can not reference other lanes yet */
/freebsd-12-stable/sys/dev/nvme/
H A Dnvme_sim.c127 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 }; local
132 lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
135 * lanes as the speed. Not 100% accurate, but may be diagnostic.
139 return link[speed] * lanes;
226 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
/freebsd-12-stable/sys/contrib/octeon-sdk/
H A Dcvmx-helper-ilk.c112 /* configure lanes and enable the link */
320 int lanes = 0; local
373 lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena);
378 result.s.speed *= lanes;
389 //cvmx_dprintf("ILK%d: link up, %d Mbps, Full duplex mode, %d lanes\n", interface, result.s.speed, lanes);
H A Dcvmx-helper-xaui.c375 int lanes; local
380 lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;
381 result.s.speed *= lanes;
/freebsd-12-stable/sys/dev/drm2/i915/
H A Dintel_bios.c532 switch (edp_link_params->lanes) {
534 dev_priv->edp.lanes = 1;
537 dev_priv->edp.lanes = 2;
541 dev_priv->edp.lanes = 4;
H A Dintel_bios.h465 u8 lanes:4; member in struct:edp_link_params
/freebsd-12-stable/sys/contrib/libsodium/test/default/
H A Dpwhash_argon2i.c19 unsigned int lanes; member in struct:__anon10730
116 unsigned int lanes; member in struct:__anon10731
H A Dpwhash_argon2id.c19 unsigned int lanes; member in struct:__anon10733
116 unsigned int lanes; member in struct:__anon10734
/freebsd-12-stable/sys/contrib/alpine-hal/
H A Dal_hal_pcie.h75 * - set number of lanes connected to the controller.
87 * - Set the max lanes width to 2 (x2)
363 struct al_pcie_gen3_lane_eq_params *eq_params; /* array of lanes params */
547 uint8_t lanes; /* Number of lanes */ member in struct:al_pcie_link_status
659 * Configure number of lanes connected to this port.
663 * @param lanes number of lanes (must be 1,2,4,8,16 and not any other value)
669 int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
H A Dal_hal_pcie.c200 * Link Mode Enable. Sets the number of lanes in the link that you want
201 * to connect to the link partner. When you have unused lanes in your
203 * the number of lanes. You must also change the value in the
1379 al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes) argument
1385 al_err("PCIe %d: already enabled, cannot set max lanes\n",
1391 active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
1399 pcie_port->max_lanes = lanes;
1700 /* if max lanes not specifies, read it from register */
1724 al_err("PCIe %d: invalid max lanes val (0x%x)\n", pcie_port->port_id, act_lanes);
1997 status->lanes
[all...]
/freebsd-12-stable/sys/dev/drm2/radeon/
H A Drv770.c1224 u32 link_width_cntl, lanes, speed_cntl, tmp; local
1257 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1260 link_width_cntl |= lanes | LC_RECONFIG_NOW |
H A Dradeon_asic.h173 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
353 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
H A Dr300.c469 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument
481 switch (lanes) {
H A Dr600.c4142 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument
4158 switch (lanes) {
4261 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; local
4308 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4311 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
/freebsd-12-stable/contrib/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp120 // same number of lanes as the input vector type. So our Predicate type
290 unsigned lanes() const { return Lanes; } function in class:__anon3549::VectorType
1071 cast<VectorType>(ExistingVector)->lanes());
1457 OS << "typedef __attribute__((neon_vector_type(" << VT->lanes() << "))) "
/freebsd-12-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c266 struct padctl_lane *lanes[8]; /* Safe maximum value. */ member in struct:padctl_pad
336 /* Define all possible mappings for USB3 port lanes */
821 " lanes: %s and %s\n", lane->name, tmp->name);
915 pad->lanes[pad->nlanes++] = lane;
962 /* Read and process associated lanes. */
963 node = ofw_bus_find_child(node, "lanes");
/freebsd-12-stable/sys/cam/nvme/
H A Dnvme_xpt.c812 sbuf_printf(&sb, " x%d (max x%d) lanes PCIe Gen%d (max Gen%d) link",
813 nvmex->lanes, nvmex->max_lanes,

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