/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | Analysis.h | 73 SmallVectorImpl<EVT> &ValueVTs, 79 SmallVectorImpl<EVT> &ValueVTs,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 288 SmallVector<EVT, 4> ValueVTs; local 289 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); 290 for (EVT VT : ValueVTs) { 372 SmallVector<EVT, 4> ValueVTs; local 373 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 376 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 377 EVT ValueVT = ValueVTs[Value]; 423 SmallVector<EVT, 1> ValueVTs; 424 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 425 assert(ValueVTs 539 SmallVector<EVT, 4> ValueVTs; local [all...] |
H A D | SelectionDAGBuilder.h | 835 SmallVector<EVT, 4> ValueVTs; member in struct:llvm::RegsForValue 837 /// The value types of the registers. This is the same size as ValueVTs and it 872 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 879 /// the result as a ValueVTs value. This uses Chain/Flag as the input and
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H A D | SelectionDAGBuilder.cpp | 776 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), 782 ComputeValueVTs(TLI, DL, Ty, ValueVTs); 786 for (EVT ValueVT : ValueVTs) { 808 if (ValueVTs.empty()) 814 SmallVector<SDValue, 4> Values(ValueVTs.size()); 816 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 818 EVT ValueVT = ValueVTs[Value]; 887 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); 900 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 973 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs 1538 SmallVector<EVT, 4> ValueVTs; local 1831 SmallVector<EVT, 4> ValueVTs, MemVTs; local 1854 SmallVector<EVT, 4> ValueVTs; local 3289 SmallVector<EVT, 4> ValueVTs; local 4072 SmallVector<EVT, 4> ValueVTs, MemVTs; local 4170 SmallVector<EVT, 4> ValueVTs; local 4209 SmallVector<EVT, 4> ValueVTs; local 4246 SmallVector<EVT, 4> ValueVTs, MemVTs; local 4888 SmallVector<EVT, 4> ValueVTs; local 6998 SmallVector<EVT, 4> ValueVTs; local 8577 SmallVector<EVT, 1> ValueVTs; local 8912 SmallVector<EVT, 3> ValueVTs; local 9164 SmallVector<EVT, 4> ValueVTs; local 9642 SmallVector<EVT, 1> ValueVTs; local 9668 SmallVector<EVT, 4> ValueVTs; local 9812 SmallVector<EVT, 1> ValueVTs; local 9840 SmallVector<EVT, 4> ValueVTs; local 10042 SmallVector<EVT, 4> ValueVTs; local [all...] |
H A D | LegalizeVectorOps.cpp | 1495 EVT ValueVTs[] = {TmpEltVT, MVT::Other}; local 1521 SDValue ScalarOp = DAG.getNode(Node->getOpcode(), dl, ValueVTs, Opers);
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H A D | LegalizeIntegerTypes.cpp | 1121 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)}; local 1124 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
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H A D | LegalizeVectorTypes.cpp | 206 EVT ValueVTs[] = {VT, MVT::Other}; local 224 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMachineFunctionInfo.cpp | 30 Type *Ty, SmallVectorImpl<MVT> &ValueVTs) { 41 ValueVTs.push_back(RegisterVT); 29 computeLegalValueVTs(const Function &F, const TargetMachine &TM, Type *Ty, SmallVectorImpl<MVT> &ValueVTs) argument
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H A D | WebAssemblyMachineFunctionInfo.h | 140 SmallVectorImpl<MVT> &ValueVTs);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 84 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, 95 ComputeValueVTs(TLI, DL, *EI, ValueVTs, MemVTs, Offsets, 104 ComputeValueVTs(TLI, DL, EltTy, ValueVTs, MemVTs, Offsets, 112 ValueVTs.push_back(TLI.getValueType(DL, Ty)); 120 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, 123 return ComputeValueVTs(TLI, DL, Ty, ValueVTs, /*MemVTs=*/nullptr, Offsets, 119 ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl<EVT> &ValueVTs, SmallVectorImpl<uint64_t> *Offsets, uint64_t StartingOffset) argument
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H A D | TargetLoweringBase.cpp | 1470 SmallVector<EVT, 4> ValueVTs; local 1471 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1472 unsigned NumValues = ValueVTs.size(); 1476 EVT VT = ValueVTs[j];
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 164 Type *Ty, SmallVectorImpl<EVT> &ValueVTs, 172 ValueVTs.push_back(EVT(MVT::i64)); 173 ValueVTs.push_back(EVT(MVT::i64)); 188 ComputePTXValueVTs(TLI, DL, EI, ValueVTs, Offsets, 212 ValueVTs.push_back(EltVT); 217 ValueVTs.push_back(VT); 235 unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs, 246 EVT EltVT = ValueVTs[Idx]; 259 if (Idx + NumElts > ValueVTs.size()) 268 if (ValueVTs[ 163 ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl<EVT> &ValueVTs, SmallVectorImpl<uint64_t> *Offsets = nullptr, uint64_t StartingOffset = 0) argument 234 CanMergeParamLoadStoresStartingAt( unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs, const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) argument 298 VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs, const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 937 SmallVector<EVT, 16> ValueVTs; local 939 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset); 941 for (unsigned Value = 0, NumValues = ValueVTs.size(); 945 EVT ArgVT = ValueVTs[Value];
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