/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MachineLocation.h | 10 // from a base address plus an offset. Register indirection can be specified by 25 unsigned Register = 0; ///< gcc/gdb register number. member in class:llvm::MachineLocation 37 : IsRegister(!Indirect), Register(R) {} 40 return IsRegister == Other.IsRegister && Register == Other.Register; 47 unsigned getReg() const { return Register; } 49 void setRegister(unsigned R) { Register = R; }
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUGlobalISelUtils.h | 12 #include "llvm/CodeGen/Register.h" 23 std::tuple<Register, unsigned, MachineInstr *> 24 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
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H A D | AMDGPUCallLowering.h | 26 Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy, 30 unsigned Align, Register DstReg) const; 33 using SplitArgTy = std::function<void(ArrayRef<Register>, LLT, LLT, int)>; 42 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const; 48 ArrayRef<Register> VRegs) const override; 51 ArrayRef<ArrayRef<Register>> VRegs) const; 54 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | AMDGPURegisterBankInfo.h | 18 #include "llvm/CodeGen/Register.h" 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 51 SmallSet<Register, 4> &SGPROperandRegs, 59 SmallSet<Register, 4> &SGPROperandRegs, 82 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 83 Register Reg) const; 85 std::pair<Register, unsigned> 86 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 97 unsigned getRegBankID(Register Re [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CombinerHelper.h | 21 #include "llvm/CodeGen/Register.h" 40 Register Addr; 41 Register Base; 42 Register Offset; 48 Register Base; 65 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const; 70 Register ToReg) const; 123 SmallVectorImpl<Register> &Ops); 127 const ArrayRef<Register> Op [all...] |
H A D | GISelKnownBits.h | 18 #include "llvm/CodeGen/Register.h" 39 virtual void computeKnownBitsImpl(Register R, KnownBits &Known, 43 unsigned computeNumSignBits(Register R, const APInt &DemandedElts, 45 unsigned computeNumSignBits(Register R, unsigned Depth = 0); 48 KnownBits getKnownBits(Register R); 51 APInt getKnownZeroes(Register R); 52 APInt getKnownOnes(Register R); 57 bool maskedValueIsZero(Register Val, const APInt &Mask) { 63 bool signBitIsZero(Register Op); 67 void computeKnownBitsForFrameIndex(Register [all...] |
H A D | CallLowering.h | 47 SmallVector<Register, 4> Regs; 51 SmallVector<Register, 2> OrigRegs; 56 ArgInfo(ArrayRef<Register> Regs, Type *Ty, 87 Register SwiftErrorVReg = 0; 128 virtual Register getStackAddress(uint64_t Size, int64_t Offset, 134 virtual void assignValueToReg(Register ValVReg, Register PhysReg, 140 virtual void assignValueToAddress(Register ValVReg, Register Addr, 155 Register extendRegiste [all...] |
H A D | MachineIRBuilder.h | 62 Register Reg; 69 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} 100 Register getReg() const { 123 Register Reg; 130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} 172 Register getReg() const { 347 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, 353 MachineInstrBuilder buildIndirectDbgValue(Register Reg, 438 Optional<MachineInstrBuilder> materializePtrAdd(Register &Res, Register Op [all...] |
H A D | LegalizationArtifactCombiner.h | 50 SmallVectorImpl<Register> &UpdatedDefs) { 54 Register DstReg = MI.getOperand(0).getReg(); 55 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); 58 Register TruncSrc; 68 Register ExtSrc; 99 SmallVectorImpl<Register> &UpdatedDefs) { 103 Register DstReg = MI.getOperand(0).getReg(); 104 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); 107 Register TruncSrc; 143 SmallVectorImpl<Register> [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | VirtRegMap.h | 1 //===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===// 52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap; 96 bool hasPhys(Register virtReg) const { 102 Register getPhys(Register virtReg) const { 109 void assignVirt2Phys(Register virtReg, MCPhysReg physReg); 113 void clearVirt(Register virtReg) { 127 bool hasPreferredPhys(Register VirtReg); 132 bool hasKnownPreference(Register VirtReg); 135 void setIsSplitFromReg(Register virtRe [all...] |
H A D | SwiftErrorValueTracking.h | 20 #include "llvm/CodeGen/Register.h" 45 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register> 51 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register> 56 llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, Register> 80 Register getOrCreateVReg(const MachineBasicBlock *, const Value *); 84 void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register); 88 Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, 93 Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *,
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H A D | Register.h | 1 //===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===// 19 class Register { class in namespace:llvm 23 Register(unsigned Val = 0): Reg(Val) {} function in class:llvm::Register 24 Register(MCRegister Val): Reg(Val) {} function in class:llvm::Register 26 // Register numbers can represent physical registers, virtual registers, and 120 bool operator==(const Register &Other) const { return Reg == Other.Reg; } 121 bool operator!=(const Register &Other) const { return Reg != Other.Reg; } 138 // Provide DenseMapInfo for Register 139 template<> struct DenseMapInfo<Register> { 146 static unsigned getHashValue(const Register [all...] |
H A D | RegisterScavenging.h | 54 Register Reg; 122 bool isRegUsed(Register Reg, bool includeReserved = true) const; 129 Register FindUnusedReg(const TargetRegisterClass *RC) const; 163 Register scavengeRegister(const TargetRegisterClass *RC, 166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, 180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC, 186 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll()); 190 bool isReserved(Register Reg) const { return MRI->isReserved(Reg); } 206 void addRegUnits(BitVector &BV, Register Reg); 209 void removeRegUnits(BitVector &BV, Register Re [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.h | 37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs, 40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs); 46 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT); 48 virtual Register getStackAddress(const CCValAssign &VA, 51 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA, 54 virtual void assignValueToAddress(Register ValVReg, 57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs, 59 unsigned ArgLocsStartIndex, Register ArgsReg, 66 ArrayRef<Register> VRegs) const override; 69 ArrayRef<ArrayRef<Register>> VReg [all...] |
H A D | MipsCallLowering.cpp | 27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA, 39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, 50 SmallVectorImpl<Register> &VRegs) { 57 SmallVector<Register, 4> VRegs; 96 void assignValueToReg(Register ValVReg, const CCValAssign &VA, 99 Register getStackAddress(const CCValAssign &VA, 102 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override; 104 bool handleSplit(SmallVectorImpl<Register> &VRegs, 106 Register ArgsReg, const EVT &VT) override; 113 void buildLoad(Register Va [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs) const override; 34 ArrayRef<ArrayRef<Register>> VRegs) const override;
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H A D | RISCVCallLowering.cpp | 26 ArrayRef<Register> VRegs) const { 39 ArrayRef<ArrayRef<Register>> VRegs) const {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 139 Register DstReg = Dst.getReg(); 140 Register SrcReg = Src.getReg(); 142 if (Register::isVirtualRegister(DstReg) && 143 Register::isVirtualRegister(SrcReg)) { 160 Register DstReg = Dst.getReg(); 161 Register SrcReg = Src2.getReg(); 177 Register DstReg = Dst.getReg(); 178 Register SrcReg = Src1.getReg(); 188 Register DstReg = Dst.getReg(); 189 Register SrcRe [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs) const override; 39 ArrayRef<ArrayRef<Register>> VRegs) const override; 46 ArrayRef<Register> VRegs,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.h | 32 ArrayRef<Register> VRegs) const override; 35 ArrayRef<ArrayRef<Register>> VRegs) const override; 42 using SplitArgTy = std::function<void(ArrayRef<Register>)>;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 86 Register VirtReg; ///< Virtual register number. 89 bool Dirty = false; ///< Register needs spill. 91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} 94 return Register::virtReg2Index(VirtReg); 132 SmallVector<Register, 16> VirtDead; 164 StringRef getPassName() const override { return "Fast Register Allocator"; } 188 SmallVectorImpl<Register> &VirtDead); 193 void killVirtReg(Register VirtReg); 195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg); 203 LiveRegMap::iterator findLiveVirtReg(Register VirtRe [all...] |
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/POSIX/ |
H A D | ProcessPOSIXLog.cpp | 30 llvm::call_once(g_once_flag, []() { Log::Register("posix", g_channel); });
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/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/SymbolFile/DWARF/ |
H A D | LogChannelDWARF.cpp | 30 Log::Register("dwarf", g_channel);
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/freebsd-12-stable/sys/dev/acpica/Osd/ |
H A D | OsdHardware.c | 101 AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value, argument 116 PciId->Function, Register, Width / 8); 124 AcpiOsWritePciConfiguration (ACPI_PCI_ID *PciId, UINT32 Register, argument 138 pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.h | 1 //===- LanaiRegisterInfo.h - Lanai Register Information Impl ----*- C++ -*-===// 45 Register getFrameRegister(const MachineFunction &MF) const override; 46 Register getBaseRegister() const;
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