Lines Matching refs:Register
86 Register VirtReg; ///< Virtual register number.
89 bool Dirty = false; ///< Register needs spill.
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
94 return Register::virtReg2Index(VirtReg);
132 SmallVector<Register, 16> VirtDead;
164 StringRef getPassName() const override { return "Fast Register Allocator"; }
188 SmallVectorImpl<Register> &VirtDead);
193 void killVirtReg(Register VirtReg);
195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
208 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
211 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint);
213 MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
214 Register Hint);
215 LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
216 Register Hint);
220 Register traceCopies(Register VirtReg) const;
221 Register traceCopyChain(Register Reg) const;
223 int getStackSpaceFor(Register VirtReg);
224 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
226 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
229 bool mayLiveOut(Register VirtReg);
230 bool mayLiveIn(Register VirtReg);
239 INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false,
248 int RegAllocFast::getStackSpaceFor(Register VirtReg) {
267 bool RegAllocFast::mayLiveOut(Register VirtReg) {
268 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
276 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
286 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
296 bool RegAllocFast::mayLiveIn(Register VirtReg) {
297 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
305 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg,
343 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg,
397 void RegAllocFast::killVirtReg(Register VirtReg) {
398 assert(Register::isVirtualRegister(VirtReg) &&
408 Register VirtReg) {
409 assert(Register::isVirtualRegister(VirtReg) &&
459 Register PhysReg = MO.getReg();
524 switch (Register VirtReg = PhysRegState[PhysReg]) {
540 switch (Register VirtReg = PhysRegState[Alias]) {
566 switch (Register VirtReg = PhysRegState[PhysReg]) {
588 switch (Register VirtReg = PhysRegState[Alias]) {
612 Register VirtReg = LR.VirtReg;
625 Register RegAllocFast::traceCopyChain(Register Reg) const {
644 Register RegAllocFast::traceCopies(Register VirtReg) const {
649 Register Reg = MI.getOperand(1).getReg();
658 return Register();
662 void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint0) {
663 const Register VirtReg = LR.VirtReg;
665 assert(Register::isVirtualRegister(VirtReg) &&
679 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
686 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
690 Hint0 = Register();
694 Register Hint1 = traceCopies(VirtReg);
700 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
707 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
711 Hint1 = Register();
754 Register VirtReg = MO.getReg();
755 assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
779 Register VirtReg, Register Hint) {
780 assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
800 assert(LRI->PhysReg && "Register not assigned");
811 Register VirtReg,
812 Register Hint) {
813 assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
846 assert(LRI->PhysReg && "Register not assigned");
866 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
888 SmallVectorImpl<Register> &VirtDead) {
890 SmallSet<Register, 8> ThroughRegs;
893 Register Reg = MO.getReg();
908 Register Reg = MO.getReg();
918 SmallVector<Register, 8> PartialDefs;
923 Register Reg = MO.getReg();
924 if (!Register::isVirtualRegister(Reg))
949 Register Reg = MO.getReg();
950 if (!Register::isVirtualRegister(Reg))
964 Register Reg = MO.getReg();
973 for (Register PartialDef : PartialDefs)
1007 assert(Register::isPhysicalRegister(i->PhysReg) && "Bad map value");
1017 Register CopySrcReg;
1018 Register CopyDstReg;
1047 Register Reg = MO.getReg();
1049 if (Register::isVirtualRegister(Reg)) {
1086 CopyDstReg = Register();
1098 Register Reg = MO.getReg();
1127 Register Reg = MO.getReg();
1142 Register Reg = MO.getReg();
1170 Register Reg = MO.getReg();
1183 Register Reg = MO.getReg();
1191 CopyDstReg = Register(); // cancel coalescing;
1200 for (Register VirtReg : VirtDead)
1218 Register Reg = MO.getReg();
1219 if (!Register::isVirtualRegister(Reg))
1238 MO.setReg(Register());