Searched refs:OperandIdx (Results 1 - 9 of 9) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 164 int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const { 170 if ((FirstIdx + OperandIdx) >= LastIdx) 173 return (int)OperandCycles[FirstIdx + OperandIdx];
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600Packetizer.cpp | 86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); local 87 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0) 136 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); local 137 if (OperandIdx < 0) 139 Register Src = MI.getOperand(OperandIdx).getReg(); 142 MI.getOperand(OperandIdx).setReg(It->second);
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H A D | R600ISelLowering.cpp | 2213 int OperandIdx[] = { local 2244 if (OperandIdx[i] < 0) 2246 SDValue &Src = Ops[OperandIdx[i] - 1]; 2250 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]); 2266 int OperandIdx[] = { local 2282 if (OperandIdx[i] < 0) 2284 SDValue &Src = Ops[OperandIdx[i] - 1]; 2289 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
H A D | DWARFDebugFrame.cpp | 216 /// Print \p Opcode's operand number \p OperandIdx which has value \p Operand. 219 unsigned OperandIdx, uint64_t Operand) const { 220 assert(OperandIdx < 2); 222 OperandType Type = getOperandTypes()[Opcode][OperandIdx]; 226 OS << " Unsupported " << (OperandIdx ? "second" : "first") << " operand to"; 217 printOperand(raw_ostream &OS, const MCRegisterInfo *MRI, bool IsEH, const Instruction &Instr, unsigned OperandIdx, uint64_t Operand) const argument
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
H A D | DWARFDebugFrame.h | 123 /// Print \p Opcode's operand number \p OperandIdx which has value \p Operand. 125 const Instruction &Instr, unsigned OperandIdx,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | RewriteStatepointsForGC.cpp | 1095 auto UpdateOperand = [&](int OperandIdx) { 1096 Value *InVal = BdvIE->getOperand(OperandIdx); 1098 BaseIE->setOperand(OperandIdx, Base); 1105 auto UpdateOperand = [&](int OperandIdx) { 1106 Value *InVal = BdvSV->getOperand(OperandIdx); 1108 BaseSV->setOperand(OperandIdx, Base);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 4831 unsigned OperandIdx[4]; local 4841 OperandIdx[SrcIdx] = Inst.size(); 4849 OperandIdx[SrcIdx] = Inst.size(); 4872 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]); 4873 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); 4874 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); 4878 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 1460 unsigned OperandIdx = 1; local 1469 ++OperandIdx;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 6558 /// Check if promoting to a vector type an operand at \p OperandIdx 6561 unsigned OperandIdx) { 6564 if (OperandIdx != 1) 6560 canCauseUndefinedBehavior(const Instruction *Use, unsigned OperandIdx) argument
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