Searched refs:MinVT (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1489 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); local
1490 if (VT.bitsLT(MinVT))
1491 VT = MinVT;
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3726 EVT MinVT = getRegisterType(Context, MVT::i32); local
3727 return VT.bitsLT(MinVT) ? MinVT : VT;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3998 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); local
3999 return VT.bitsLT(MinVT) ? MinVT : VT;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3259 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); local
3260 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
3262 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
3267 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
H A DDAGCombiner.cpp9943 EVT MinVT = N0.getValueType(); local
9951 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
9963 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
18190 EVT MinVT = SVT; local
18198 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT;
18209 Opnds.append(NumElts, DAG.getUNDEF(MinVT));
18218 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i)));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2891 EVT MinVT = getRegisterType(Context, ReturnMVT); local
2892 return VT.bitsLT(MinVT) ? MinVT : VT;
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