/freebsd-12-stable/lib/libc/quad/TESTS/ |
H A D | Makefile | 5 MUL= mul.c ../muldi3.c macro 6 mul: ${MUL} 7 gcc -g -DSPARC_XXX ${MUL} -o ${.TARGET}
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/freebsd-12-stable/contrib/byacc/test/yacc/ |
H A D | quote_calc.tab.h | 6 #define MUL 262 macro
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H A D | quote_calc2.tab.h | 6 #define MUL 262 macro
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H A D | quote_calc.tab.c | 154 #define MUL 262 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 154 #define MUL 262 macro 272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 286 "expr : expr \"MUL\" expr",
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/freebsd-12-stable/contrib/byacc/test/btyacc/ |
H A D | quote_calc.tab.h | 9 #define MUL 262 macro
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H A D | quote_calc2.tab.h | 9 #define MUL 262 macro
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/freebsd-12-stable/sys/contrib/libsodium/src/libsodium/crypto_onetimeauth/poly1305/donna/ |
H A D | poly1305_donna64.h | 8 #define MUL(out, x, y) out = ((uint128_t) x * y) macro 96 MUL(d0, h0, r0); 97 MUL(d, h1, s2); 99 MUL(d, h2, s1); 101 MUL(d1, h0, r1); 102 MUL(d, h1, r0); 104 MUL(d, h2, s2); 106 MUL(d2, h0, r2); 107 MUL(d, h1, r1); 109 MUL( [all...] |
/freebsd-12-stable/contrib/bearssl/src/hash/ |
H A D | ghash_ctmul.c | 65 uint64_t mul32tmp = MUL(x, y); \ 180 z0 = MUL(x0, y0) ^ MUL(x1, y3) ^ MUL(x2, y2) ^ MUL(x3, y1); 181 z1 = MUL(x0, y1) ^ MUL(x1, y0) ^ MUL(x2, y3) ^ MUL(x3, y2); 182 z2 = MUL(x [all...] |
/freebsd-12-stable/contrib/bearssl/src/int/ |
H A D | i32_montmul.c | 50 z = (uint64_t)d[v + 1] + MUL(xu, y[v + 1]) + r1; 53 z = (uint64_t)t + MUL(f, m[v + 1]) + r2;
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H A D | i32_fmont.c | 43 z = (uint64_t)x[v + 1] + MUL(f, m[v + 1]) + cc;
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H A D | i32_mulacc.c | 50 z = (uint64_t)d[1 + u + v] + MUL(f, a[1 + v]) + cc;
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H A D | i32_muladd.c | 113 zl = MUL(mw, q) + cc;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 3582 // 32b Opcodes that can be combined with a MUL 3601 // 64b Opcodes that can be combined with a MUL 3660 // Opcodes that can be combined with a MUL 4151 /// F|MUL I=A,B,0 4161 /// the F|MUL. In the example above IdxMulOpd is 1. 4177 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); local 4179 Register SrcReg0 = MUL->getOperand(1).getReg(); 4180 bool Src0IsKill = MUL->getOperand(1).isKill(); 4181 Register SrcReg1 = MUL->getOperand(2).getReg(); 4182 bool Src1IsKill = MUL 4328 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); local 4367 MachineInstr *MUL; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiTargetTransformInfo.h | 92 case ISD::MUL:
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetTransformInfo.cpp | 129 case ISD::MUL:
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/freebsd-12-stable/contrib/byacc/test/ |
H A D | btyacc_demo.y | 22 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; 174 | expr '*' expr($e) { $$ = build_expr($1, MUL, $3); }
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 215 { ISD::MUL, MVT::v2i64, 17 }, 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 487 { ISD::MUL, MVT::v2i64, 1 }, 488 { ISD::MUL, MVT::v4i64, 1 }, 489 { ISD::MUL, MVT::v8i64, 1 } 514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MV [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 582 if (Shl_0.getOpcode() == ISD::MUL) { 1614 case ISD::MUL: 1703 if (Opcode == ISD::MUL && 1770 if (Val.getOpcode() != ISD::MUL || 1798 if (Val.getOpcode() == ISD::MUL) { 1821 if (V.getOpcode() == ISD::MUL) { 1838 if (V.getOpcode() == ISD::MUL) { 1940 // SHL nodes will be converted to MUL nodes 1942 NOpcode = ISD::MUL; 1989 (Child.getOpcode() == ISD::MUL || Chil [all...] |
H A D | HexagonISelLoweringHVX.cpp | 91 setOperationAction(ISD::MUL, T, Custom); 150 setOperationAction(ISD::MUL, T, Custom); 699 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV); 760 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV); 927 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, 987 ByteIdx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, 1305 // For i16 there is V6_vmpyih, which acts exactly like the MUL opcode. 1542 case ISD::MUL: 1577 case ISD::MUL: return LowerHvxMul(Op, DAG);
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator in enum:llvm::ISD::NodeType
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGAddressAnalysis.cpp | 236 // MUL instruction. In this case Base is the actual BASE pointer. 240 if (Base->getOperand(1)->getOpcode() == ISD::MUL)
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H A D | TargetLowering.cpp | 1985 case ISD::MUL: 2541 // TODO: There are more binop opcodes that could be handled here - MUL, MIN, 2583 case ISD::MUL: 4691 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor); 4780 // FIXME: We should support doing a MUL in a wider type. 4795 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor); 4900 // FIXME: We should support doing a MUL in a wider type. 5015 // If MUL is unavailable, we cannot proceed in any case. 5016 if (!isOperationLegalOrCustom(ISD::MUL, VT)) 5154 SDValue Op0 = DAG.getNode(ISD::MUL, D [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 599 if (OtherOp.getOpcode() == ISD::MUL) { 609 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) { 619 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) { 637 if (N->getOperand(0).getOpcode() == ISD::MUL) { 640 } else if (N->getOperand(1).getOpcode() == ISD::MUL) { 685 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); 686 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 115 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 189 setOperationAction(ISD::MUL, MVT::i64, Legal); 191 setOperationAction(ISD::MUL, MVT::i64, Custom); 211 setTargetDAGCombine(ISD::MUL); 232 setOperationAction(ISD::MUL, MVT::i32, Legal); 279 setOperationAction(ISD::MUL, MVT::i64, Legal); 337 setOperationAction(ISD::MUL, Ty, Legal); 458 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 1037 case ISD::MUL: 2003 DAG.getNode(ISD::MUL, SDLo [all...] |