Lines Matching refs:MUL
1985 case ISD::MUL:
2541 // TODO: There are more binop opcodes that could be handled here - MUL, MIN,
2583 case ISD::MUL:
4691 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
4780 // FIXME: We should support doing a MUL in a wider type.
4795 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
4900 // FIXME: We should support doing a MUL in a wider type.
5015 // If MUL is unavailable, we cannot proceed in any case.
5016 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5154 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5255 // If MUL is unavailable, we cannot proceed in any case.
5256 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5396 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5743 assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
5776 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
5801 if (Opcode != ISD::MUL) {
5810 if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
5813 // TODO non-MUL case?
5848 if (Opcode == ISD::MUL) {
5849 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
5850 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
6392 (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) ||
6428 DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
6980 Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale);
7025 Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
7199 if (isOperationLegalOrCustom(ISD::MUL, VT))
7200 return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7242 Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7503 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
7512 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
7522 // We can fall back to a libcall with an illegal type for the MUL if we
7618 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;