Searched refs:LiveRegs (Results 1 - 25 of 30) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h51 RegisterSet LiveRegs;
59 LiveRegs.setUniverse(TRI.getNumRegs());
68 LiveRegs.clear();
69 LiveRegs.setUniverse(TRI.getNumRegs());
73 void clear() { LiveRegs.clear(); }
76 bool empty() const { return LiveRegs.empty(); }
84 LiveRegs.insert(*SubRegs);
93 LiveRegs.erase(*R);
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); }
151 const_iterator begin() const { return LiveRegs
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H A DReachingDefAnalysis.h46 LiveRegsDefInfo LiveRegs;
143 /// Set up LiveRegs by merging predecessor live-out values.
H A DExecutionDomainFix.h120 LiveRegsDVInfo LiveRegs;
170 /// Set LiveRegs[rx] = dv, updating reference counts.
186 /// Set up LiveRegs by merging predecessor live-out values.
H A DScheduleDAGInstrs.h252 LivePhysRegs LiveRegs; member in class:llvm::ScheduleDAGInstrs
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp72 assert(!LiveRegs.empty() && "Must enter basic block first.");
74 if (LiveRegs[rx] == dv)
76 if (LiveRegs[rx])
77 release(LiveRegs[rx]);
78 LiveRegs[rx] = retain(dv);
83 assert(!LiveRegs.empty() && "Must enter basic block first.");
84 if (!LiveRegs[rx])
87 release(LiveRegs[rx]);
88 LiveRegs[rx] = nullptr;
93 assert(!LiveRegs
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H A DLivePhysRegs.cpp33 RegisterSet::iterator LRI = LiveRegs.begin();
34 while (LRI != LiveRegs.end()) {
38 LRI = LiveRegs.erase(LRI);
141 if (LiveRegs.count(Reg))
146 if (LiveRegs.count(*R))
152 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
171 /// Adds all callee saved registers to \p LiveRegs.
172 static void addCalleeSavedRegs(LivePhysRegs &LiveRegs, argument
176 LiveRegs.addReg(*CSR);
242 void llvm::computeLiveIns(LivePhysRegs &LiveRegs, argument
253 addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs) argument
281 LivePhysRegs LiveRegs; local
322 computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB) argument
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H A DReachingDefAnalysis.cpp35 // Set up LiveRegs to represent registers entering MBB.
37 if (LiveRegs.empty())
38 LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal);
47 LiveRegs[*Unit] = -1;
48 MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit]);
67 LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]);
68 if ((LiveRegs[Unit] != ReachingDefDefaultVal))
69 MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit]);
80 assert(!LiveRegs
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H A DStackMapLivenessAnalysis.cpp52 LivePhysRegs LiveRegs; member in class:__anon4663::StackMapLiveness
128 LiveRegs.init(*TRI);
130 LiveRegs.addLiveOutsNoPristines(MBB);
141 LLVM_DEBUG(dbgs() << " " << LiveRegs << " " << *I);
142 LiveRegs.stepBackward(*I);
164 for (auto Reg : LiveRegs)
H A DRegisterPressure.cpp256 LiveRegs.clear();
289 LiveRegs.init(*MRI);
326 P.LiveInRegs.reserve(LiveRegs.size());
327 LiveRegs.appendTo(P.LiveInRegs);
338 P.LiveOutRegs.reserve(LiveRegs.size());
339 LiveRegs.appendTo(P.LiveOutRegs);
345 assert(LiveRegs.size() == 0 && "no region boundary");
707 LaneBitmask PrevMask = LiveRegs.insert(P);
746 LaneBitmask LiveMask = LiveRegs.contains(Reg);
752 LaneBitmask LiveMask = LiveRegs
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H A DScheduleDAGInstrs.cpp1091 static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs, argument
1101 bool IsKill = LiveRegs.available(MRI, Reg);
1104 LiveRegs.addReg(Reg);
1111 LiveRegs.init(*TRI);
1112 LiveRegs.addLiveOuts(MBB);
1130 LiveRegs.removeReg(Reg);
1132 LiveRegs.removeRegsInMask(MO);
1138 toggleKills(MRI, LiveRegs, MI, true);
1142 toggleKills(MRI, LiveRegs, MI, false);
1152 toggleKills(MRI, LiveRegs, *
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H A DBranchRelaxation.cpp85 LivePhysRegs LiveRegs; member in class:__anon4522::BranchRelaxation
272 computeAndAddLiveIns(LiveRegs, *NewBB);
337 computeAndAddLiveIns(LiveRegs, *NewBB);
H A DBranchFolding.h133 LivePhysRegs LiveRegs; member in class:llvm::BranchFolder
H A DBranchFolding.cpp370 LiveRegs.clear();
371 LiveRegs.addLiveOuts(OldMBB);
376 LiveRegs.stepBackward(*I);
388 if (!LiveRegs.available(*MRI, Reg))
430 computeAndAddLiveIns(LiveRegs, *NewMBB);
895 LiveRegs.init(*TRI);
900 LiveRegs.clear();
901 LiveRegs.addLiveOuts(*Pred);
904 if (!LiveRegs.available(*MRI, Reg))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h104 LiveRegSet LiveRegs; member in class:llvm::GCNRPTracker
116 const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
128 decltype(LiveRegs) moveLiveRegs() {
129 return std::move(LiveRegs);
132 static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
142 void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
166 bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
254 Range &&LiveRegs) {
256 for (const auto &RM : LiveRegs)
253 getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs) argument
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H A DGCNRegPressure.cpp278 GCNRPTracker::LiveRegSet LiveRegs;
285 LiveRegs[Reg] = LiveMask;
287 return LiveRegs;
296 if (&LiveRegs != LiveRegsCopy)
297 LiveRegs = *LiveRegsCopy;
299 LiveRegs = After ? getLiveRegsAfter(MI, LIS)
303 MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
324 auto LiveMask = LiveRegs[U.RegUnit];
335 auto I = LiveRegs.find(Reg);
336 if (I == LiveRegs
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H A DSIFrameLowering.cpp51 LivePhysRegs &LiveRegs,
57 LiveRegs.addReg(CSRegs[i]);
63 if (!MRI.isPhysRegUsed(Reg) && LiveRegs.available(MRI, Reg))
68 if (LiveRegs.available(MRI, Reg))
83 LivePhysRegs LiveRegs; local
84 LiveRegs.init(*MRI.getTargetRegisterInfo());
86 MRI, LiveRegs, AMDGPU::SReg_32_XM0_XEXECRegClass, true);
92 static void buildPrologSpill(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB, argument
121 MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
140 static void buildEpilogReload(LivePhysRegs &LiveRegs, MachineBasicBloc argument
50 findScratchNonCalleeSaveRegister(MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs, const TargetRegisterClass &RC, bool Unused = false) argument
692 LivePhysRegs LiveRegs; local
832 LivePhysRegs LiveRegs; local
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H A DSIMachineScheduler.cpp1614 DAG->fillVgprSgprCost(LiveRegs.begin(), LiveRegs.end(),
1626 : LiveRegs) dbgs()
1688 (void) LiveRegs.insert(Reg);
1696 std::set<unsigned>::iterator Pos = LiveRegs.find(Reg);
1697 assert (Pos != LiveRegs.end() && // Reg must be live.
1702 LiveRegs.erase(Pos);
H A DSIMachineScheduler.h327 std::set<unsigned> LiveRegs; member in class:llvm::SIScheduleBlockScheduler
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp147 LivePhysRegs LiveRegs; member in class:__anon5450::FixupBWInstPass
170 LiveRegs.init(TII->getRegisterInfo());
206 if (!LiveRegs.contains(SuperDestReg)) {
214 if (!LiveRegs.contains(getX86SubSuperRegister(OrigDestReg, 16)) &&
215 !LiveRegs.contains(getX86SubSuperRegister(SuperDestReg, 8,
436 LiveRegs.clear();
438 LiveRegs.addLiveOuts(MBB);
450 LiveRegs.stepBackward(*MI);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp171 LivePhysRegs LiveRegs(TII->getRegisterInfo());
172 LiveRegs.addLiveOuts(MBB);
174 LiveRegs.stepBackward(*I);
181 for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
188 for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
H A DSystemZShortenInst.cpp52 LivePhysRegs LiveRegs; member in class:__anon5370::SystemZShortenInst
89 if (LiveRegs.contains(OtherReg))
144 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
183 LiveRegs.clear();
184 LiveRegs.addLiveOuts(MBB);
337 LiveRegs.stepBackward(MI);
350 LiveRegs.init(*TRI);
H A DSystemZElimCompare.cpp703 LivePhysRegs LiveRegs(*TRI);
704 LiveRegs.addLiveOuts(MBB);
705 bool CompleteCCUsers = !LiveRegs.contains(SystemZ::CC);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp241 LivePhysRegs LiveRegs; local
242 computeAndAddLiveIns(LiveRegs, *DoneBB);
243 computeAndAddLiveIns(LiveRegs, *StoreBB);
244 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
247 computeAndAddLiveIns(LiveRegs, *StoreBB);
249 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
334 LivePhysRegs LiveRegs; local
335 computeAndAddLiveIns(LiveRegs, *DoneBB);
336 computeAndAddLiveIns(LiveRegs, *StoreBB);
337 computeAndAddLiveIns(LiveRegs, *LoadCmpB
392 LivePhysRegs LiveRegs; local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp389 LivePhysRegs LiveRegs; local
390 computeAndAddLiveIns(LiveRegs, *LoopMBB);
391 computeAndAddLiveIns(LiveRegs, *DoneMBB);
519 LivePhysRegs LiveRegs; local
520 computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
521 computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB);
522 computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
523 computeAndAddLiveIns(LiveRegs, *DoneMBB);
616 LivePhysRegs LiveRegs; local
617 computeAndAddLiveIns(LiveRegs, *LoopHeadMB
657 LivePhysRegs LiveRegs; local
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp191 LivePhysRegs LiveRegs; local
192 computeAndAddLiveIns(LiveRegs, *loop1MBB);
193 computeAndAddLiveIns(LiveRegs, *loop2MBB);
194 computeAndAddLiveIns(LiveRegs, *sinkMBB);
195 computeAndAddLiveIns(LiveRegs, *exitMBB);
292 LivePhysRegs LiveRegs; local
293 computeAndAddLiveIns(LiveRegs, *loop1MBB);
294 computeAndAddLiveIns(LiveRegs, *loop2MBB);
295 computeAndAddLiveIns(LiveRegs, *exitMBB);
566 LivePhysRegs LiveRegs; local
809 LivePhysRegs LiveRegs; local
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