| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 70 bool getMemOperandWithOffset(const MachineInstr &LdSt,
75 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
|
| H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
762 if (LdSt.getNumOperands() != 4)
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
768 switch (LdSt.getOpcode()) {
789 BaseOp = &LdSt.getOperand(1);
790 Offset = LdSt.getOperand(2).getImm();
798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, argument
757 getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo * ) const argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 563 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
565 if (!LdSt.mayLoadOrStore())
571 if (LdSt.getNumExplicitOperands() != 3)
573 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
576 if (!LdSt.hasOneMemOperand())
579 Width = (*LdSt.memoperands_begin())->getSize();
580 BaseReg = &LdSt.getOperand(1);
581 Offset = LdSt.getOperand(2).getImm();
562 getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const argument
|
| H A D | RISCVInstrInfo.h | 89 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, argument
265 if (!LdSt.mayLoadOrStore())
268 unsigned Opc = LdSt.getOpcode();
270 if (isDS(LdSt)) {
272 getNamedOperand(LdSt, AMDGPU::OpName::offset);
275 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
290 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
292 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
302 if (LdSt.mayLoad())
303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt,
[all...] |
| H A D | SIInstrInfo.h | 184 bool getMemOperandWithOffset(const MachineInstr &LdSt,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1981 bool AArch64InstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, argument
1985 if (!LdSt.mayLoadOrStore())
1989 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI);
1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
1995 assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
1997 if (LdSt.getNumExplicitOperands() == 3) {
1999 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
2000 !LdSt.getOperand(2).isImm())
2002 } else if (LdSt
1992 getMemOperandWithOffsetWidth( const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const argument
[all...] |
| H A D | AArch64InstrInfo.h | 125 /// Return the immediate offset of the base register in a load/store \p LdSt.
126 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 207 bool getMemOperandWithOffset(const MachineInstr &LdSt,
|
| H A D | HexagonInstrInfo.cpp | 2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2947 BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2943 getMemOperandWithOffset( const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 362 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
|
| H A D | PPCInstrInfo.cpp | 4264 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
4266 if (!LdSt.mayLoadOrStore())
4270 if (LdSt.getNumExplicitOperands() != 3)
4272 if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4275 if (!LdSt.hasOneMemOperand())
4278 Width = (*LdSt.memoperands_begin())->getSize();
4279 Offset = LdSt.getOperand(1).getImm();
4280 BaseReg = &LdSt.getOperand(2);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 294 bool getMemOperandWithOffset(const MachineInstr &LdSt,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1044 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); local
1045 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1050 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
|