Searched refs:LC1 (Results 1 - 8 of 8) sorted by relevance
| /freebsd-12-stable/sys/dev/xdma/controller/ |
| H A D | pl330.h | 65 #define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */ macro
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.h | 107 Hexagon::LC1 == R);
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| H A D | HexagonMCChecker.cpp | 49 Defs[Hexagon::LC1].insert(Unconditional);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 153 Reserved.set(Hexagon::LC1); // C3
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| H A D | HexagonHardwareLoops.cpp | 999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
1000 static const unsigned Regs1[] = { LC1, SA1 };
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| H A D | HexagonISelLowering.cpp | 301 .Case("lc1", Hexagon::LC1)
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 308 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; local
313 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
319 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
325 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
331 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
337 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
343 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
351 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
360 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
372 LC1
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 650 /* 0 */ SA0, LC0, SA1, LC1,
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