1/*- 2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33#ifndef _DEV_XDMA_CONTROLLER_PL330_H_ 34#define _DEV_XDMA_CONTROLLER_PL330_H_ 35 36/* pl330 registers */ 37#define DSR 0x000 /* DMA Manager Status */ 38#define DPC 0x004 /* DMA Program Counter */ 39#define INTEN 0x020 /* Interrupt Enable */ 40#define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */ 41#define INTMIS 0x028 /* Interrupt Status */ 42#define INTCLR 0x02C /* Interrupt Clear */ 43#define FSRD 0x030 /* Fault Status DMA Manager */ 44#define FSRC 0x034 /* Fault Status DMA Channel */ 45#define FTRD 0x038 /* Fault Type DMA Manager */ 46#define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */ 47#define CSR(n) (0x100 + 0x08 * (n)) /* Channel status for DMA channel n */ 48#define CPC(n) (0x104 + 0x08 * (n)) /* Channel PC for DMA channel n */ 49#define SAR(n) (0x400 + 0x20 * (n)) /* Source address for DMA channel n */ 50#define DAR(n) (0x404 + 0x20 * (n)) /* Destination address for DMA channel n */ 51#define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */ 52#define CCR_DST_BURST_SIZE_S 15 53#define CCR_DST_BURST_SIZE_1 (0 << CCR_DST_BURST_SIZE_S) 54#define CCR_DST_BURST_SIZE_2 (1 << CCR_DST_BURST_SIZE_S) 55#define CCR_DST_BURST_SIZE_4 (2 << CCR_DST_BURST_SIZE_S) 56#define CCR_SRC_BURST_SIZE_S 1 57#define CCR_SRC_BURST_SIZE_1 (0 << CCR_SRC_BURST_SIZE_S) 58#define CCR_SRC_BURST_SIZE_2 (1 << CCR_SRC_BURST_SIZE_S) 59#define CCR_SRC_BURST_SIZE_4 (2 << CCR_SRC_BURST_SIZE_S) 60#define CCR_DST_INC (1 << 14) 61#define CCR_SRC_INC (1 << 0) 62#define CCR_DST_PROT_CTRL_S 22 63#define CCR_DST_PROT_PRIV (1 << CCR_DST_PROT_CTRL_S) 64#define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */ 65#define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */ 66 67#define DBGSTATUS 0xD00 /* Debug Status */ 68#define DBGCMD 0xD04 /* Debug Command */ 69#define DBGINST0 0xD08 /* Debug Instruction-0 */ 70#define DBGINST1 0xD0C /* Debug Instruction-1 */ 71#define CR0 0xE00 /* Configuration Register 0 */ 72#define CR1 0xE04 /* Configuration Register 1 */ 73#define CR2 0xE08 /* Configuration Register 2 */ 74#define CR3 0xE0C /* Configuration Register 3 */ 75#define CR4 0xE10 /* Configuration Register 4 */ 76#define CRD 0xE14 /* DMA Configuration */ 77#define WD 0xE80 /* Watchdog Register */ 78 79#define R_SAR 0 80#define R_CCR 1 81#define R_DAR 2 82 83/* 84 * 0xFE0- 0xFEC periph_id_n RO Configuration-dependent Peripheral Identification Registers 85 * 0xFF0- 0xFFC pcell_id_n RO Configuration-dependent Component Identification Registers 86 */ 87 88/* pl330 ISA */ 89#define DMAADDH 0x54 90#define DMAADNH 0x5c 91#define DMAEND 0x00 92#define DMAFLUSHP 0x35 93#define DMAGO 0xa0 94#define DMAKILL 0x01 95#define DMALD 0x04 96#define DMALDP 0x25 97#define DMALP 0x20 98#define DMALPEND 0x28 99#define DMALPEND_NF (1 << 4) /* DMALP started the loop */ 100/* 101 * TODO: documentation miss opcode for infinite loop 102 * #define DMALPFE 0 103 */ 104#define DMAMOV 0xbc 105#define DMANOP 0x18 106#define DMARMB 0x12 107#define DMASEV 0x34 108#define DMAST 0x08 109#define DMASTP 0x29 110#define DMASTZ 0x0c 111#define DMAWFE 0x36 112#define DMAWFP 0x30 113#define DMAWMB 0x13 114 115#endif /* !_DEV_XDMA_CONTROLLER_PL330_H_ */ 116