Searched refs:JZ_SRBC (Results 1 - 2 of 2) sorted by relevance

/freebsd-12-stable/sys/mips/ingenic/
H A Djz4780_clock.c752 reg = CSR_READ_4(sc, JZ_SRBC);
754 CSR_WRITE_4(sc, JZ_SRBC, reg);
758 reg = CSR_READ_4(sc, JZ_SRBC);
760 CSR_WRITE_4(sc, JZ_SRBC, reg);
H A Djz4780_regs.h339 #define JZ_SRBC 0x000000c4 /* Soft Reset & Bus Control */ macro

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