1/* $NetBSD: ingenic_regs.h,v 1.22 2015/10/08 17:54:30 macallan Exp $ */ 2 3/*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef JZ4780_REGS_H 32#define JZ4780_REGS_H 33 34/* for mips_wbflush() */ 35#include <machine/locore.h> 36 37/* UARTs, mostly 16550 compatible with 32bit spaced registers */ 38#define JZ_UART0 0x10030000 39#define JZ_UART1 0x10031000 40#define JZ_UART2 0x10032000 41#define JZ_UART3 0x10033000 42#define JZ_UART4 0x10034000 43 44/* LCD controller base addresses, registers are in jzfb_regs.h */ 45#define JZ_LCDC0_BASE 0x13050000 46#define JZ_LCDC1_BASE 0x130a0000 47 48/* TCU unit base address */ 49#define JZ_TCU_BASE 0x10002000 50 51/* Watchdog */ 52#define JZ_WDOG_TDR 0x00000000 /* compare */ 53#define JZ_WDOG_TCER 0x00000004 54 #define TCER_ENABLE 0x01 /* enable counter */ 55#define JZ_WDOG_TCNT 0x00000008 /* 16bit up count */ 56#define JZ_WDOG_TCSR 0x0000000c 57 #define TCSR_PCK_EN 0x01 /* PCLK */ 58 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 59 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 60 #define TCSR_PRESCALE_M 0x38 61 #define TCSR_DIV_1 0x00 62 #define TCSR_DIV_4 0x08 63 #define TCSR_DIV_16 0x10 64 #define TCSR_DIV_64 0x18 65 #define TCSR_DIV_256 0x20 66 #define TCSR_DIV_1024 0x28 67 68/* timers and PWMs */ 69#define JZ_TC_TER 0x00000010 /* TC enable reg, ro */ 70#define JZ_TC_TESR 0x00000014 /* TC enable set reg. */ 71 #define TESR_TCST0 0x0001 /* enable counter 0 */ 72 #define TESR_TCST1 0x0002 /* enable counter 1 */ 73 #define TESR_TCST2 0x0004 /* enable counter 2 */ 74 #define TESR_TCST3 0x0008 /* enable counter 3 */ 75 #define TESR_TCST4 0x0010 /* enable counter 4 */ 76 #define TESR_TCST5 0x0020 /* enable counter 5 */ 77 #define TESR_TCST6 0x0040 /* enable counter 6 */ 78 #define TESR_TCST7 0x0080 /* enable counter 7 */ 79 #define TESR_OST 0x8000 /* enable OST */ 80#define JZ_TC_TECR 0x00000018 /* TC enable clear reg. */ 81#define JZ_TC_TFR 0x00000020 82 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 83 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 84 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 85 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 86 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 87 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 88 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 89 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 90 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 91#define JZ_TC_TFSR 0x00000024 /* timer flag set */ 92#define JZ_TC_TFCR 0x00000028 /* timer flag clear */ 93#define JZ_TC_TMR 0x00000030 /* timer flag mask */ 94 #define TMR_FMASK(n) (1 << (n)) 95 #define TMR_HMASK(n) (1 << ((n) + 16)) 96#define JZ_TC_TMSR 0x00000034 /* timer flag mask set */ 97#define JZ_TC_TMCR 0x00000038 /* timer flag mask clear*/ 98 99#define JZ_TC_TDFR(n) (0x00000040 + (n * 0x10)) /* FULL compare */ 100#define JZ_TC_TDHR(n) (0x00000044 + (n * 0x10)) /* HALF compare */ 101#define JZ_TC_TCNT(n) (0x00000048 + (n * 0x10)) /* count */ 102 103#define JZ_TC_TCSR(n) (0x0000004c + (n * 0x10)) 104/* same bits as in JZ_WDOG_TCSR */ 105 106/* operating system timer */ 107#define JZ_OST_DATA 0x000000e0 /* compare */ 108#define JZ_OST_CNT_LO 0x000000e4 109#define JZ_OST_CNT_HI 0x000000e8 110#define JZ_OST_CTRL 0x000000ec 111 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 112 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 113 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 114 #define OSTC_PRESCALE_M 0x0038 115 #define OSTC_DIV_1 0x0000 116 #define OSTC_DIV_4 0x0008 117 #define OSTC_DIV_16 0x0010 118 #define OSTC_DIV_64 0x0018 119 #define OSTC_DIV_256 0x0020 120 #define OSTC_DIV_1024 0x0028 121 #define OSTC_SHUTDOWN 0x0200 122 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 123#define JZ_OST_CNT_U32 0x000000fc /* copy of CNT_HI when reading CNT_LO */ 124 125static inline void 126writereg(uint32_t reg, uint32_t val) 127{ 128 *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 129 mips_wbflush(); 130} 131 132static inline uint32_t 133readreg(uint32_t reg) 134{ 135 mips_wbflush(); 136 return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg); 137} 138 139/* Clock management */ 140#define JZ_CGU_BASE 0x10000000 141 142#define JZ_CPCCR 0x00000000 /* Clock Control Register */ 143 #define JZ_PDIV_M 0x000f0000 /* PCLK divider mask */ 144 #define JZ_PDIV_S 16 /* PCLK divider shift */ 145 #define JZ_CDIV_M 0x0000000f /* CPU clock divider mask */ 146 #define JZ_CDIV_S 0 /* CPU clock divider shift */ 147#define JZ_CPAPCR 0x00000010 /* APLL */ 148#define JZ_CPMPCR 0x00000014 /* MPLL */ 149#define JZ_CPEPCR 0x00000018 /* EPLL */ 150#define JZ_CPVPCR 0x0000001C /* VPLL */ 151 #define JZ_PLLM_S 19 /* PLL multiplier shift */ 152 #define JZ_PLLM_M 0xfff80000 /* PLL multiplier mask */ 153 #define JZ_PLLN_S 13 /* PLL divider shift */ 154 #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */ 155 #define JZ_PLLP_S 9 /* PLL postdivider shift */ 156 #define JZ_PLLP_M 0x00001700 /* PLL postdivider mask */ 157 #define JZ_PLLON 0x00000010 /* PLL is on and stable */ 158 #define JZ_PLLBP 0x00000002 /* PLL bypass */ 159 #define JZ_PLLEN 0x00000001 /* PLL enable */ 160#define JZ_CLKGR0 0x00000020 /* Clock Gating Registers */ 161 #define CLK_NEMC (1 << 0) 162 #define CLK_BCH (1 << 1) 163 #define CLK_OTG0 (1 << 2) 164 #define CLK_MSC0 (1 << 3) 165 #define CLK_SSI0 (1 << 4) 166 #define CLK_SMB0 (1 << 5) 167 #define CLK_SMB1 (1 << 6) 168 #define CLK_SCC (1 << 7) 169 #define CLK_AIC (1 << 8) 170 #define CLK_TSSI0 (1 << 9) 171 #define CLK_OWI (1 << 10) 172 #define CLK_MSC1 (1 << 11) 173 #define CLK_MSC2 (1 << 12) 174 #define CLK_KBC (1 << 13) 175 #define CLK_SADC (1 << 14) 176 #define CLK_UART0 (1 << 15) 177 #define CLK_UART1 (1 << 16) 178 #define CLK_UART2 (1 << 17) 179 #define CLK_UART3 (1 << 18) 180 #define CLK_SSI1 (1 << 19) 181 #define CLK_SSI2 (1 << 20) 182 #define CLK_PDMA (1 << 21) 183 #define CLK_GPS (1 << 22) 184 #define CLK_MAC (1 << 23) 185 #define CLK_UHC (1 << 24) 186 #define CLK_SMB2 (1 << 25) 187 #define CLK_CIM (1 << 26) 188 #define CLK_TVE (1 << 27) 189 #define CLK_LCD (1 << 28) 190 #define CLK_IPU (1 << 29) 191 #define CLK_DDR0 (1 << 30) 192 #define CLK_DDR1 (1 << 31) 193#define JZ_CLKGR1 0x00000028 /* Clock Gating Registers */ 194 #define CLK_SMB3 (1 << 0) 195 #define CLK_TSSI1 (1 << 1) 196 #define CLK_VPU (1 << 2) 197 #define CLK_PCM (1 << 3) 198 #define CLK_GPU (1 << 4) 199 #define CLK_COMPRESS (1 << 5) 200 #define CLK_AIC1 (1 << 6) 201 #define CLK_GPVLC (1 << 7) 202 #define CLK_OTG1 (1 << 8) 203 #define CLK_HDMI (1 << 9) 204 #define CLK_UART4 (1 << 10) 205 #define CLK_AHB_MON (1 << 11) 206 #define CLK_SMB4 (1 << 12) 207 #define CLK_DES (1 << 13) 208 #define CLK_X2D (1 << 14) 209 #define CLK_P1 (1 << 15) 210#define JZ_DDCDR 0x0000002c /* DDR clock divider register */ 211#define JZ_VPUCDR 0x00000030 /* VPU clock divider register */ 212#define JZ_I2SCDR 0x00000060 /* I2S device clock divider register */ 213#define JZ_I2S1CDR 0x000000a0 /* I2S device clock divider register */ 214#define JZ_USBCDR 0x00000050 /* OTG PHY clock divider register */ 215#define JZ_LP0CDR 0x00000054 /* LCD0 pix clock divider register */ 216#define JZ_LP1CDR 0x00000064 /* LCD1 pix clock divider register */ 217#define JZ_MSC0CDR 0x00000068 /* MSC0 clock divider register */ 218#define JZ_MSC1CDR 0x000000a4 /* MSC1 clock divider register */ 219#define JZ_MSC2CDR 0x000000a8 /* MSC2 clock divider register */ 220 #define MSCCDR_SCLK_A 0x40000000 221 #define MSCCDR_MPLL 0x80000000 222 #define MSCCDR_CE 0x20000000 223 #define MSCCDR_BUSY 0x10000000 224 #define MSCCDR_STOP 0x08000000 225 #define MSCCDR_PHASE 0x00008000 /* 0 - 90deg phase, 1 - 180 */ 226 #define MSCCDR_DIV_M 0x000000ff /* src / ((div + 1) * 2) */ 227 #define UHCCDR_DIV_M 0x000000ff 228#define JZ_UHCCDR 0x0000006c /* UHC 48M clock divider register */ 229 #define UHCCDR_SCLK_A 0x00000000 230 #define UHCCDR_MPLL 0x40000000 231 #define UHCCDR_EPLL 0x80000000 232 #define UHCCDR_OTG_PHY 0xc0000000 233 #define UHCCDR_CLK_MASK 0xc0000000 234 #define UHCCDR_CE 0x20000000 235 #define UHCCDR_BUSY 0x10000000 236 #define UHCCDR_STOP 0x08000000 237 #define UHCCDR_DIV_M 0x000000ff 238 #define UHCCDR_DIV(d) (d) 239#define JZ_SSICDR 0x00000074 /* SSI clock divider register */ 240#define JZ_CIMCDR 0x0000007c /* CIM MCLK clock divider register */ 241#define JZ_PCMCDR 0x00000084 /* PCM device clock divider register */ 242#define JZ_GPUCDR 0x00000088 /* GPU clock divider register */ 243#define JZ_HDMICDR 0x0000008c /* HDMI clock divider register */ 244#define JZ_BCHCDR 0x000000ac /* BCH clock divider register */ 245#define JZ_CPM_INTR 0x000000b0 /* CPM interrupt register */ 246#define JZ_CPM_INTRE 0x000000b4 /* CPM interrupt enable register */ 247#define JZ_CPSPR 0x00000034 /* CPM scratch register */ 248#define JZ_CPSRPR 0x00000038 /* CPM scratch protected register */ 249#define JZ_USBPCR 0x0000003c /* USB parameter control register */ 250 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 251 #define PCR_AVLD_REG 0x40000000 252 #define PCR_IDPULLUP_MASK 0x30000000 253 #define PCR_INCR_MASK 0x08000000 254 #define PCR_TCRISETUNE 0x04000000 255 #define PCR_COMMONONN 0x02000000 256 #define PCR_VBUSVLDEXT 0x01000000 257 #define PCR_VBUSVLDEXTSEL 0x00800000 258 #define PCR_POR 0x00400000 259 #define PCR_SIDDQ 0x00200000 260 #define PCR_OTG_DISABLE 0x00100000 261 #define PCR_COMPDISTN_M 0x000e0000 262 #define PCR_OTGTUNE 0x0001c000 263 #define PCR_SQRXTUNE 0x00003800 264 #define PCR_TXFSLSTUNE 0x00000780 265 #define PCR_TXPREEMPHTUNE 0x00000040 266 #define PCR_TXHSXVTUNE 0x00000030 267 #define PCR_TXVREFTUNE 0x0000000f 268#define JZ_USBRDT 0x00000040 /* Reset detect timer register */ 269 #define USBRDT_USBRDT_SHIFT 0 270 #define USBRDT_USBRDT_WIDTH 23 271 #define USBRDT_VBFIL_LD_EN 0x01000000 272#define JZ_USBVBFIL 0x00000044 /* USB jitter filter register */ 273 #define USBVBFIL_IDDIGFIL_SHIFT 16 274 #define USBVBFIL_IDDIGFIL_WIDTH 16 275 #define USBVBFIL_USBVBFIL_SHIFT 0 276 #define USBVBFIL_USBVBFIL_WIDTH 16 277#define JZ_USBPCR1 0x00000048 /* USB parameter control register 1 */ 278 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 279 #define PCR_REFCLK_CORE 0x08000000 280 #define PCR_REFCLK_XO25 0x04000000 281 #define PCR_REFCLK_CO 0x00000000 282 #define PCR_REFCLK_M 0x0c000000 283 #define PCR_CLK_M 0x03000000 /* clock */ 284 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 285 #define PCR_CLK_48 0x02000000 /* 48MHz */ 286 #define PCR_CLK_24 0x01000000 /* 24MHz */ 287 #define PCR_CLK_12 0x00000000 /* 12MHz */ 288 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 289 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 290 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 291 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 292 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 293 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 294 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 295 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 296 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 297 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 298 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 299 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 300 #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */ 301 302/* power manager */ 303#define JZ_LPCR 0x00000004 304 #define LPCR_PD_SCPU (1u << 31) /* CPU1 power down */ 305 #define LPCR_PD_VPU (1u << 30) /* VPU power down */ 306 #define LPCR_PD_GPU (1u << 29) /* GPU power down */ 307 #define LPCR_PD_GPS (1u << 28) /* GPS power down */ 308 #define LPCR_SCPUS (1u << 27) /* CPU1 power down status */ 309 #define LPCR_VPUS (1u << 26) /* VPU power down status */ 310 #define LPCR_GPUS (1u << 25) /* GPU power down status */ 311 #define LPCR_GPSS (1u << 24) /* GPS power down status */ 312 #define LPCR_GPU_IDLE (1u << 20) /* GPU idle status */ 313 #define LPCR_PST_SHIFT 8 /* Power stability time */ 314 #define LPCR_PST_MASK (0xFFFu << 8) 315 #define LPCR_DUTY_SHIFT 3 /* CPU clock duty */ 316 #define LPCR_DUTY_MASK (0x1Fu << 3) 317 #define LPCR_DOZE (1u << 2) /* Doze mode */ 318 #define LPCR_LPM_SHIFT 0 /* Low power mode */ 319 #define LPCR_LPM_MASK (0x03u << 0) 320 321#define JZ_OPCR 0x00000024 /* Oscillator Power Control Reg. */ 322 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 323 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 324 #define OPCR_L2CM_M 0x0c000000 325 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 326 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 327 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 328 #define OPCR_SPENDN0 0x00000080 /* 0 - OTG port forced down */ 329 #define OPCR_SPENDN1 0x00000040 /* 0 - UHC port forced down */ 330 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 331 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 332 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 333 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 334 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 335 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 336 337#define JZ_SPCR0 0x000000b8 /* SRAM Power Control Registers */ 338#define JZ_SPCR1 0x000000bc 339#define JZ_SRBC 0x000000c4 /* Soft Reset & Bus Control */ 340 #define SRBC_UHC_SR 0x00004000 /* UHC soft reset*/ 341 342/* 343 * random number generator 344 * 345 * Its function currently isn't documented by Ingenic. 346 * However, testing suggests that it works as expected. 347 */ 348#define JZ_ERNG 0x000000d8 349#define JZ_RNG 0x000000dc 350 351/* Interrupt controller */ 352#define JZ_ICBASE 0x10001000 /* IC base address */ 353#define JZ_ICSR0 0x00000000 /* raw IRQ line status */ 354#define JZ_ICMR0 0x00000004 /* IRQ mask, 1 masks IRQ */ 355#define JZ_ICMSR0 0x00000008 /* sets bits in mask register */ 356#define JZ_ICMCR0 0x0000000c /* clears bits in mask register */ 357#define JZ_ICPR0 0x00000010 /* line status after masking */ 358 359#define JZ_ICSR1 0x00000020 /* raw IRQ line status */ 360#define JZ_ICMR1 0x00000024 /* IRQ mask, 1 masks IRQ */ 361#define JZ_ICMSR1 0x00000028 /* sets bits in mask register */ 362#define JZ_ICMCR1 0x0000002c /* clears bits in maks register */ 363#define JZ_ICPR1 0x00000030 /* line status after masking */ 364 365#define JZ_DSR0 0x00000034 /* source for PDMA */ 366#define JZ_DMR0 0x00000038 /* mask for PDMA */ 367#define JZ_DPR0 0x0000003c /* pending for PDMA */ 368 369#define JZ_DSR1 0x00000040 /* source for PDMA */ 370#define JZ_DMR1 0x00000044 /* mask for PDMA */ 371#define JZ_DPR1 0x00000048 /* pending for PDMA */ 372 373/* memory controller */ 374#define JZ_DMMAP0 0x13010024 375#define JZ_DMMAP1 0x13010028 376 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 377 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 378 * constant */ 379/* USB controllers */ 380#define JZ_EHCI_BASE 0x13490000 381#define JZ_EHCI_REG_UTMI_BUS 0x000000b0 382 #define UTMI_BUS_WIDTH 0x00000040 383#define JZ_OHCI_BASE 0x134a0000 384 385#define JZ_DWC2_BASE 0x13500000 386#define JZ_DWC2_GUSBCFG 0 387 388/* Ethernet */ 389#define JZ_DME_BASE 0x16000000 390#define JZ_DME_IO 0 391#define JZ_DME_DATA 2 392 393/* GPIO */ 394#define JZ_GPIO_A_BASE 0x10010000 395#define JZ_GPIO_B_BASE 0x10010100 396#define JZ_GPIO_C_BASE 0x10010200 397#define JZ_GPIO_D_BASE 0x10010300 398#define JZ_GPIO_E_BASE 0x10010400 399#define JZ_GPIO_F_BASE 0x10010500 400 401/* GPIO registers per port */ 402#define JZ_GPIO_PIN 0x00000000 /* pin level register */ 403/* 0 - normal gpio, 1 - interrupt */ 404#define JZ_GPIO_INT 0x00000010 /* interrupt register */ 405#define JZ_GPIO_INTS 0x00000014 /* interrupt set register */ 406#define JZ_GPIO_INTC 0x00000018 /* interrupt clear register */ 407/* 408 * INT == 1: 1 disables interrupt 409 * INT == 0: device select, see below 410 */ 411#define JZ_GPIO_MASK 0x00000020 /* port mask register */ 412#define JZ_GPIO_MASKS 0x00000024 /* port mask set register */ 413#define JZ_GPIO_MASKC 0x00000028 /* port mask clear register */ 414/* 415 * INT == 1: 0 - level triggered, 1 - edge triggered 416 * INT == 0: 0 - device select, see below 417 */ 418#define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */ 419#define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */ 420#define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */ 421/* 422 * INT == 1: 423 * PAT1 == 0: 0 - trigger on low, 1 - trigger on high 424 * PAT0 == 1: 0 - trigger on falling edge, 1 - trigger on rising edge 425 * INT == 0: 426 * MASK == 0: 427 * PAT1 == 0: 0 - device 0, 1 - device 1 428 * PAT0 == 1: 0 - device 2, 1 - device 3 429 * MASK == 1: 430 * PAT1 == 0: set gpio output 431 * PAT1 == 1: pin is input 432 */ 433#define JZ_GPIO_PAT0 0x00000040 /* pattern 0 register */ 434#define JZ_GPIO_PAT0S 0x00000044 /* pattern 0 set register */ 435#define JZ_GPIO_PAT0C 0x00000048 /* pattern 0 clear register */ 436/* 1 - interrupt happened */ 437#define JZ_GPIO_FLAG 0x00000050 /* flag register */ 438#define JZ_GPIO_FLAGC 0x00000058 /* flag clear register */ 439/* 1 - disable pull up/down resistors */ 440#define JZ_GPIO_DPULL 0x00000070 /* pull disable register */ 441#define JZ_GPIO_DPULLS 0x00000074 /* pull disable set register */ 442#define JZ_GPIO_DPULLC 0x00000078 /* pull disable clear register */ 443/* the following are uncommented in the manual */ 444#define JZ_GPIO_DRVL 0x00000080 /* drive low register */ 445#define JZ_GPIO_DRVLS 0x00000084 /* drive low set register */ 446#define JZ_GPIO_DRVLC 0x00000088 /* drive low clear register */ 447#define JZ_GPIO_DIR 0x00000090 /* direction register */ 448#define JZ_GPIO_DIRS 0x00000094 /* direction register */ 449#define JZ_GPIO_DIRC 0x00000098 /* direction register */ 450#define JZ_GPIO_DRVH 0x000000a0 /* drive high register */ 451#define JZ_GPIO_DRVHS 0x000000a4 /* drive high set register */ 452#define JZ_GPIO_DRVHC 0x000000a8 /* drive high clear register */ 453 454/* I2C / SMBus */ 455#define JZ_SMB0_BASE 0x10050000 456#define JZ_SMB1_BASE 0x10051000 457#define JZ_SMB2_BASE 0x10052000 458#define JZ_SMB3_BASE 0x10053000 459#define JZ_SMB4_BASE 0x10054000 460 461/* SMBus register offsets, per port */ 462#define JZ_SMBCON 0x00 /* SMB control */ 463 #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ 464 #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ 465 #define JZ_REST 0x20 /* 1 - allow RESTART */ 466 #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ 467 #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ 468 #define JZ_SPD_M 0x06 /* bus speed control */ 469 #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ 470 #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ 471 #define JZ_MD 0x01 /* enable master */ 472#define JZ_SMBTAR 0x04 /* SMB target address */ 473 #define JZ_SMATP 0x1000 /* enable 10bit master addr */ 474 #define JZ_SPECIAL 0x0800 /* 1 - special command */ 475 #define JZ_START 0x0400 /* 1 - send START */ 476 #define JZ_SMBTAR_M 0x03ff /* target address */ 477#define JZ_SMBSAR 0x08 /* SMB slave address */ 478#define JZ_SMBDC 0x10 /* SMB data buffer and command */ 479 #define JZ_CMD 0x100 /* 1 - read, 0 - write */ 480 #define JZ_DATA 0x0ff 481#define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ 482#define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ 483#define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ 484#define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ 485#define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ 486 #define JZ_ISTT 0x400 /* START or RESTART occured */ 487 #define JZ_ISTP 0x200 /* STOP occured */ 488 #define JZ_TXABT 0x40 /* ABORT occured */ 489 #define JZ_TXEMP 0x10 /* TX FIFO is low */ 490 #define JZ_TXOF 0x08 /* TX FIFO is high */ 491 #define JZ_RXFL 0x04 /* RX FIFO is at JZ_SMBRXTL*/ 492 #define JZ_RXOF 0x02 /* RX FIFO is high */ 493 #define JZ_RXUF 0x01 /* RX FIFO underflow */ 494#define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ 495#define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ 496#define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ 497#define JZ_SMBCINT 0x40 /* Clear Interrupts */ 498 #define JZ_CLEARALL 0x01 499#define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ 500#define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ 501#define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ 502#define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ 503#define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ 504#define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ 505#define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ 506#define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ 507#define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ 508#define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ 509#define JZ_SMBENB 0x6C /* SMB Enable */ 510 #define JZ_ENABLE 0x01 511#define JZ_SMBST 0x70 /* SMB Status register */ 512 #define JZ_SLVACT 0x40 /* slave is active */ 513 #define JZ_MSTACT 0x20 /* master is active */ 514 #define JZ_RFF 0x10 /* RX FIFO is full */ 515 #define JZ_RFNE 0x08 /* RX FIFO not empty */ 516 #define JZ_TFE 0x04 /* TX FIFO is empty */ 517 #define JZ_TFNF 0x02 /* TX FIFO is not full */ 518 #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ 519#define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ 520#define JZ_SMBDMACR 0x88 /* DMA Control Register */ 521#define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ 522#define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ 523#define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ 524#define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ 525#define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ 526#define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ 527 #define JZ_HDENB 0x100 /* enable hold time */ 528 529/* SD/MMC hosts */ 530#define JZ_MSC0_BASE 0x13450000 531#define JZ_MSC1_BASE 0x13460000 532#define JZ_MSC2_BASE 0x13470000 533 534#define JZ_MSC_CTRL 0x00 535 #define JZ_SEND_CCSD 0x8000 536 #define JZ_SEND_AS_CCSD 0x4000 537 #define JZ_EXIT_MULTIPLE 0x0080 538 #define JZ_EXIT_TRANSFER 0x0040 539 #define JZ_START_READWAIT 0x0020 540 #define JZ_STOP_READWAIT 0x0010 541 #define JZ_RESET 0x0008 542 #define JZ_START_OP 0x0004 543 #define JZ_CLOCK_CTRL_M 0x0003 544 #define JZ_CLOCK_START 0x0002 545 #define JZ_CLOCK_STOP 0x0001 546#define JZ_MSC_STAT 0x04 547 #define JZ_AUTO_CMD12_DONE 0x80000000 548 #define JZ_AUTO_CMD23_DONE 0x40000000 549 #define JZ_SVS 0x20000000 550 #define JZ_PIN_LEVEL_M 0x1f000000 551 #define JZ_BCE 0x00100000 /* boot CRC error */ 552 #define JZ_BDE 0x00080000 /* boot data end */ 553 #define JZ_BAE 0x00040000 /* boot acknowledge error */ 554 #define JZ_BAR 0x00020000 /* boot ack. received */ 555 #define JZ_DMAEND 0x00010000 556 #define JZ_IS_RESETTING 0x00008000 557 #define JZ_SDIO_INT_ACTIVE 0x00004000 558 #define JZ_PRG_DONE 0x00002000 559 #define JZ_DATA_TRAN_DONE 0x00001000 560 #define JZ_END_CMD_RES 0x00000800 561 #define JZ_DATA_FIFO_AFULL 0x00000400 562 #define JZ_IS_READWAIT 0x00000200 563 #define JZ_CLK_EN 0x00000100 564 #define JZ_DATA_FIFO_FULL 0x00000080 565 #define JZ_DATA_FIFO_EMPTY 0x00000040 566 #define JZ_CRC_RES_ERR 0x00000020 567 #define JZ_CRC_READ_ERR 0x00000010 568 #define JZ_CRC_WRITE_ERR_M 0x0000000c 569 #define JZ_CRC_WRITE_OK 0x00000000 570 #define JZ_CRC_CARD_ERR 0x00000004 571 #define JZ_CRC_NO_STATUS 0x00000008 572 #define JZ_TIME_OUT_RES 0x00000002 573 #define JZ_TIME_OUT_READ 0x00000001 574#define JZ_MSC_CLKRT 0x08 575 #define JZ_DEV_CLK 0x0 576 #define JZ_DEV_CLK_2 0x1 /* DEV_CLK / 2 */ 577 #define JZ_DEV_CLK_4 0x2 /* DEV_CLK / 4 */ 578 #define JZ_DEV_CLK_8 0x3 /* DEV_CLK / 8 */ 579 #define JZ_DEV_CLK_16 0x4 /* DEV_CLK / 16 */ 580 #define JZ_DEV_CLK_32 0x5 /* DEV_CLK / 32 */ 581 #define JZ_DEV_CLK_64 0x6 /* DEV_CLK / 64 */ 582 #define JZ_DEV_CLK_128 0x7 /* DEV_CLK / 128 */ 583#define JZ_MSC_CMDAT 0x0c 584 #define JZ_CCS_EXPECTED 0x80000000 585 #define JZ_READ_CEATA 0x40000000 586 #define JZ_DIS_BOOT 0x08000000 587 #define JZ_ENA_BOOT 0x04000000 588 #define JZ_EXP_BOOT_ACK 0x02000000 589 #define JZ_BOOT_MODE 0x01000000 590 #define JZ_AUTO_CMD23 0x00040000 591 #define JZ_SDIO_PRDT 0x00020000 592 #define JZ_AUTO_CMD12 0x00010000 593 #define JZ_RTRG_M 0x0000c000 /* receive FIFO trigger */ 594 #define JZ_RTRG_16 0x00000000 /* >= 16 */ 595 #define JZ_RTRG_32 0x00004000 /* >= 32 */ 596 #define JZ_RTRG_64 0x00008000 /* >= 64 */ 597 #define JZ_RTRG_96 0x0000c000 /* >= 96 */ 598 #define JZ_TTRG_M 0x00003000 /* transmit FIFO trigger */ 599 #define JZ_TTRG_16 0x00000000 /* >= 16 */ 600 #define JZ_TTRG_32 0x00001000 /* >= 32 */ 601 #define JZ_TTRG_64 0x00002000 /* >= 64 */ 602 #define JZ_TTRG_96 0x00003000 /* >= 96 */ 603 #define JZ_IO_ABORT 0x00000800 604 #define JZ_BUS_WIDTH_M 0x00000600 605 #define JZ_BUS_1BIT 0x00000000 606 #define JZ_BUS_4BIT 0x00000400 607 #define JZ_BUS_8BIT 0x00000600 608 #define JZ_INIT 0x00000080 /* send 80 clk init before cmd */ 609 #define JZ_BUSY 0x00000040 610 #define JZ_STREAM 0x00000020 611 #define JZ_WRITE 0x00000010 /* read otherwise */ 612 #define JZ_DATA_EN 0x00000008 613 #define JZ_RESPONSE_M 0x00000007 /* response format */ 614 #define JZ_RES_NONE 0x00000000 615 #define JZ_RES_R1 0x00000001 /* R1 and R1b */ 616 #define JZ_RES_R2 0x00000002 617 #define JZ_RES_R3 0x00000003 618 #define JZ_RES_R4 0x00000004 619 #define JZ_RES_R5 0x00000005 620 #define JZ_RES_R6 0x00000006 621 #define JZ_RES_R7 0x00000007 622#define JZ_MSC_RESTO 0x10 /* 16bit response timeout in MSC_CLK */ 623#define JZ_MSC_RDTO 0x14 /* 32bit read timeout in MSC_CLK */ 624#define JZ_MSC_BLKLEN 0x18 /* 16bit block length */ 625#define JZ_MSC_NOB 0x1c /* 16bit block counter */ 626#define JZ_MSC_SNOB 0x20 /* 16bit successful block counter */ 627#define JZ_MSC_IMASK 0x24 /* interrupt mask */ 628 #define JZ_INT_AUTO_CMD23_DONE 0x40000000 629 #define JZ_INT_SVS 0x20000000 630 #define JZ_INT_PIN_LEVEL_M 0x1f000000 631 #define JZ_INT_BCE 0x00100000 632 #define JZ_INT_BDE 0x00080000 633 #define JZ_INT_BAE 0x00040000 634 #define JZ_INT_BAR 0x00020000 635 #define JZ_INT_DMAEND 0x00010000 636 #define JZ_INT_AUTO_CMD12_DONE 0x00008000 637 #define JZ_INT_DATA_FIFO_FULL 0x00004000 638 #define JZ_INT_DATA_FIFO_EMPTY 0x00002000 639 #define JZ_INT_CRC_RES_ERR 0x00001000 640 #define JZ_INT_CRC_READ_ERR 0x00000800 641 #define JZ_INT_CRC_WRITE_ERR 0x00000400 642 #define JZ_INT_TIMEOUT_RES 0x00000200 643 #define JZ_INT_TIMEOUT_READ 0x00000100 644 #define JZ_INT_SDIO 0x00000080 645 #define JZ_INT_TXFIFO_WR_REQ 0x00000040 646 #define JZ_INT_RXFIFO_RD_REQ 0x00000020 647 #define JZ_INT_END_CMD_RES 0x00000004 648 #define JZ_INT_PRG_DONE 0x00000002 649 #define JZ_INT_DATA_TRAN_DONE 0x00000001 650#define JZ_MSC_IFLG 0x28 /* interrupt flags */ 651#define JZ_MSC_CMD 0x2c /* 6bit CMD index */ 652#define JZ_MSC_ARG 0x30 /* 32bit argument */ 653#define JZ_MSC_RES 0x34 /* 8x16bit response data FIFO */ 654#define JZ_MSC_RXFIFO 0x38 655#define JZ_MSC_TXFIFO 0x3c 656#define JZ_MSC_LPM 0x40 657 #define JZ_DRV_SEL_M 0xc0000000 658 #define JZ_FALLING_EDGE 0x00000000 659 #define JZ_RISING_1NS 0x40000000 /* 1ns delay */ 660 #define JZ_RISING_4 0x80000000 /* 1/4 MSC_CLK delay */ 661 #define JZ_SMP_SEL 0x20000000 /* 1 - rising edge */ 662 #define JZ_LPM 0x00000001 /* low power mode */ 663#define JZ_MSC_DMAC 0x44 664 #define JZ_MODE_SEL 0x80 /* 1 - specify transfer length */ 665 #define JZ_AOFST_M 0x60 /* address offset in bytes */ 666 #define JZ_AOFST_S 6 /* addrress offset shift */ 667 #define JZ_ALIGNEN 0x10 /* allow non-32bit-aligned transfers */ 668 #define JZ_INCR_M 0x0c /* burst type */ 669 #define JZ_INCR_16 0x00 670 #define JZ_INCR_32 0x04 671 #define JZ_INCR_64 0x08 672 #define JZ_DMASEL 0x02 /* 1 - SoC DMAC, 0 - MSC built-in */ 673 #define JZ_DMAEN 0x01 /* enable DMA */ 674#define JZ_MSC_DMANDA 0x48 /* next descriptor paddr */ 675#define JZ_MSC_DMADA 0x4c /* current descriptor */ 676#define JZ_MSC_DMALEN 0x50 /* transfer tength */ 677#define JZ_MSC_DMACMD 0x54 678 #define JZ_DMA_IDI_M 0xff000000 679 #define JZ_DMA_ID_M 0x00ff0000 680 #define JZ_DMA_AOFST_M 0x00000600 681 #define JZ_DMA_ALIGN 0x00000100 682 #define JZ_DMA_ENDI 0x00000002 683 #define JZ_DMA_LINK 0x00000001 684#define JZ_MSC_CTRL2 0x58 685 #define JZ_PIP 0x1f000000 /* 1 - intr trigger on high */ 686 #define JZ_RST_EN 0x00800000 687 #define JZ_STPRM 0x00000010 688 #define JZ_SVC 0x00000008 689 #define JZ_SMS_M 0x00000007 690 #define JZ_SMS_DEF 0x00000000 /* default speed */ 691 #define JZ_SMS_HIGH 0x00000001 /* high speed */ 692 #define JZ_SMS_SDR12 0x00000002 693 #define JZ_SMS_SDR25 0x00000003 694 #define JZ_SMS_SDR50 0x00000004 695#define JZ_MSC_RTCNT 0x5c /* RT FIFO count */ 696 697/* EFUSE Slave Interface */ 698#define JZ_EFUSE 0x134100D0 699#define JZ_EFUCTRL 0x00 700 #define JZ_EFUSE_BANK 0x40000000 /* select upper 4KBit */ 701 #define JZ_EFUSE_ADDR_M 0x3fe00000 /* in bytes */ 702 #define JZ_EFUSE_ADDR_SHIFT 21 703 #define JZ_EFUSE_SIZE_M 0x001f0000 /* in bytes */ 704 #define JZ_EFUSE_SIZE_SHIFT 16 705 #define JZ_EFUSE_PROG 0x00008000 /* enable programming */ 706 #define JZ_EFUSE_WRITE 0x00000002 /* write enable */ 707 #define JZ_EFUSE_READ 0x00000001 /* read enable */ 708#define JZ_EFUCFG 0x04 709 #define JZ_EFUSE_INT_E 0x80000000 /* which IRQ? */ 710 #define JZ_EFUSE_RD_ADJ_M 0x00f00000 711 #define JZ_EFUSE_RD_STROBE 0x000f0000 712 #define JZ_EFUSE_WR_ADJUST 0x0000f000 713 #define JZ_EFUSE_WR_STROBE 0x00000fff 714#define JZ_EFUSTATE 0x08 715 #define JZ_EFUSE_GLOBAL_P 0x00008000 /* wr protect bits */ 716 #define JZ_EFUSE_CHIPID_P 0x00004000 717 #define JZ_EFUSE_CUSTID_P 0x00002000 718 #define JZ_EFUSE_SECWR_EN 0x00001000 719 #define JZ_EFUSE_PC_P 0x00000800 720 #define JZ_EFUSE_HDMIKEY_P 0x00000400 721 #define JZ_EFUSE_SECKEY_P 0x00000200 722 #define JZ_EFUSE_SECBOOT_EN 0x00000100 723 #define JZ_EFUSE_HDMI_BUSY 0x00000004 724 #define JZ_EFUSE_WR_DONE 0x00000002 725 #define JZ_EFUSE_RD_DONE 0x00000001 726#define JZ_EFUDATA0 0x0C 727#define JZ_EFUDATA1 0x10 728#define JZ_EFUDATA2 0x14 729#define JZ_EFUDATA3 0x18 730#define JZ_EFUDATA4 0x1C 731#define JZ_EFUDATA5 0x20 732#define JZ_EFUDATA6 0x24 733#define JZ_EFUDATA7 0x28 734 735/* NEMC */ 736#define JZ_NEMC_BASE 0x13410000 737#define JZ_NEMC_SMCR(n) (0x10 + (n) * 4) 738 739# define JZ_NEMC_SMCR_SMT_SHIFT 0 740# define JZ_NEMC_SMCR_SMT_WIDTH 1 741# define JZ_NEMC_SMCR_SMT_MASK (((1 << JZ_NEMC_SMCR_SMT_WIDTH) - 1) << JZ_NEMC_SMCR_SMT_SHIFT) 742# define JZ_NEMC_SMCR_SMT_NORMAL (0 << JZ_NEMC_SMCR_SMT_SHIFT) 743# define JZ_NEMC_SMCR_SMT_BROM (1 << JZ_NEMC_SMCR_SMT_SHIFT) 744 745# define JZ_NEMC_SMCR_BL_SHIFT 1 746# define JZ_NEMC_SMCR_BL_WIDTH 2 747# define JZ_NEMC_SMCR_BL_MASK (((1 << JZ_NEMC_SMCR_BL_WIDTH) - 1) << JZ_NEMC_SMCR_BL_SHIFT) 748# define JZ_NEMC_SMCR_BL(n) (((n) << JZ_NEMC_SMCR_BL_SHIFT) 749 750# define JZ_NEMC_SMCR_BW_SHIFT 6 751# define JZ_NEMC_SMCR_BW_WIDTH 2 752# define JZ_NEMC_SMCR_BW_MASK (((1 << JZ_NEMC_SMCR_BW_WIDTH) - 1) << JZ_NEMC_SMCR_BW_SHIFT) 753# define JZ_NEMC_SMCR_BW_8 (0 << JZ_NEMC_SMCR_BW_SHIFT) 754 755# define JZ_NEMC_SMCR_TAS_SHIFT 8 756# define JZ_NEMC_SMCR_TAS_WIDTH 4 757# define JZ_NEMC_SMCR_TAS_MASK (((1 << JZ_NEMC_SMCR_TAS_WIDTH) - 1) << JZ_NEMC_SMCR_TAS_SHIFT) 758 759# define JZ_NEMC_SMCR_TAH_SHIFT 12 760# define JZ_NEMC_SMCR_TAH_WIDTH 4 761# define JZ_NEMC_SMCR_TAH_MASK (((1 << JZ_NEMC_SMCR_TAH_WIDTH) - 1) << JZ_NEMC_SMCR_TAH_SHIFT) 762 763# define JZ_NEMC_SMCR_TBP_SHIFT 16 764# define JZ_NEMC_SMCR_TBP_WIDTH 4 765# define JZ_NEMC_SMCR_TBP_MASK (((1 << JZ_NEMC_SMCR_TBP_WIDTH) - 1) << JZ_NEMC_SMCR_TBP_SHIFT) 766 767# define JZ_NEMC_SMCR_TAW_SHIFT 20 768# define JZ_NEMC_SMCR_TAW_WIDTH 4 769# define JZ_NEMC_SMCR_TAW_MASK (((1 << JZ_NEMC_SMCR_TAW_WIDTH) - 1) << JZ_NEMC_SMCR_TAW_SHIFT) 770 771# define JZ_NEMC_SMCR_STRV_SHIFT 24 772# define JZ_NEMC_SMCR_STRV_WIDTH 4 773# define JZ_NEMC_SMCR_STRV_MASK (((1 << JZ_NEMC_SMCR_STRV_WIDTH) - 1) << JZ_NEMC_SMCR_STRV_SHIFT) 774 775#define JZ_NEMC_SACR(n) (0x30 + (n) * 4) 776 777# define JZ_NEMC_SACR_MASK_SHIFT 0 778# define JZ_NEMC_SACR_MASK_WIDTH 8 779# define JZ_NEMC_SACR_MASK_MASK (((1 << JZ_NEMC_SACR_MASK_WIDTH) - 1) << JZ_NEMC_SACR_MASK_SHIFT) 780 781# define JZ_NEMC_SACR_ADDR_SHIFT 0 782# define JZ_NEMC_SACR_ADDR_WIDTH 8 783# define JZ_NEMC_SACR_ADDR_MASK (((1 << JZ_NEMC_SACR_ADDR_WIDTH) - 1) << JZ_NEMC_SACR_ADDR_SHIFT) 784 785#define JC_NEMC_NFSCR 0x50 786 787#endif /* JZ4780_REGS_H */ 788