Searched refs:JZ_MSC0CDR (Results 1 - 2 of 2) sorted by relevance
| /freebsd-12-stable/sys/mips/ingenic/ |
| H A D | jz4780_clock.c | 252 MUX(JZ_MSC0CDR, 30, 2, 0x6),
260 DIV(JZ_MSC0CDR, 0, 1, 8, 29, 28, 27),
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| H A D | jz4780_regs.h | 217 #define JZ_MSC0CDR 0x00000068 /* MSC0 clock divider register */ macro
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