Searched refs:JZ_LP0CDR (Results 1 - 2 of 2) sorted by relevance

/freebsd-12-stable/sys/mips/ingenic/
H A Djz4780_clock.c238 MUX(JZ_LP0CDR, 30, 2, 0xe),
239 DIV(JZ_LP0CDR, 0, 0, 8, 28, 27, 26),
H A Djz4780_regs.h215 #define JZ_LP0CDR 0x00000054 /* LCD0 pix clock divider register */ macro

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