Searched refs:IntermediateVT (Results 1 - 10 of 10) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp937 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, argument
966 IntermediateVT = NewVT;
1310 MVT IntermediateVT; local
1313 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1376 EVT &IntermediateVT,
1390 IntermediateVT = RegisterEVT;
1422 IntermediateVT = NewVT;
1375 getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h36 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
H A DSIISelLowering.cpp845 EVT VT, EVT &IntermediateVT,
853 IntermediateVT = RegisterVT;
860 IntermediateVT = RegisterVT;
870 IntermediateVT = RegisterVT;
877 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
843 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h829 EVT &IntermediateVT,
837 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
839 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
836 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp374 EVT IntermediateVT; local
381 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
385 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
403 PartVT, IntermediateVT, V);
412 PartVT, IntermediateVT, V);
418 EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(),
419 (IntermediateVT.isVector()
420 ? IntermediateVT.getVectorNumElements() * NumParts
422 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
708 EVT IntermediateVT; local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h303 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
H A DMipsISelLowering.cpp132 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
136 IntermediateVT = RegisterVT;
131 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1247 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
H A DX86ISelLowering.cpp2137 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2146 IntermediateVT = MVT::i1;
2155 IntermediateVT = MVT::v32i1;
2160 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2136 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8028 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; local
8051 Arrange = DAG.getBitcast(IntermediateVT, Arrange);
8052 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange,
8055 Extend = DAG.getNode(ExtendOp, dl, IntermediateVT, Arrange);

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