/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 937 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, argument 966 IntermediateVT = NewVT; 1310 MVT IntermediateVT; local 1313 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1376 EVT &IntermediateVT, 1390 IntermediateVT = RegisterEVT; 1422 IntermediateVT = NewVT; 1375 getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.h | 36 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
|
H A D | SIISelLowering.cpp | 845 EVT VT, EVT &IntermediateVT, 853 IntermediateVT = RegisterVT; 860 IntermediateVT = RegisterVT; 870 IntermediateVT = RegisterVT; 877 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); 843 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
|
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 829 EVT &IntermediateVT, 837 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 839 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, 836 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 374 EVT IntermediateVT; local 381 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT, 385 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 403 PartVT, IntermediateVT, V); 412 PartVT, IntermediateVT, V); 418 EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(), 419 (IntermediateVT.isVector() 420 ? IntermediateVT.getVectorNumElements() * NumParts 422 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS 708 EVT IntermediateVT; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 303 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
|
H A D | MipsISelLowering.cpp | 132 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 136 IntermediateVT = RegisterVT; 131 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument
|
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 1247 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
|
H A D | X86ISelLowering.cpp | 2137 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 2146 IntermediateVT = MVT::i1; 2155 IntermediateVT = MVT::v32i1; 2160 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, 2136 getVectorTypeBreakdownForCallingConv( LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8028 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; local 8051 Arrange = DAG.getBitcast(IntermediateVT, Arrange); 8052 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, 8055 Extend = DAG.getNode(ExtendOp, dl, IntermediateVT, Arrange);
|