Searched refs:FMA (Results 1 - 25 of 33) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.h320 bool FMA; member in class:llvm::GCNSubtarget
550 return FMA;
1224 bool FMA; member in class:llvm::final
1309 bool hasFMA() const { return FMA; }
H A DSIISelLowering.cpp521 setOperationAction(ISD::FMA, MVT::f16, Legal);
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
726 setTargetDAGCombine(ISD::FMA);
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
3884 // free fneg'd operands. As long as we have fast FMA (controlled by
4087 case ISD::FMA:
7627 case ISD::FMA:
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, S
9757 SDValue FMA = N->getOperand(2); local
[all...]
H A DAMDGPUSubtarget.cpp537 FMA(false),
H A DAMDGPUISelLowering.cpp420 setOperationAction(ISD::FMA, VT, Expand);
516 case ISD::FMA:
590 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
2599 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
3734 case ISD::FMA:
H A DAMDGPUISelDAGToDAG.cpp905 case ISD::FMA:
2104 bool IsFMA = N->getOpcode() == ISD::FMA;
H A DR600ISelLowering.cpp226 setOperationAction(ISD::FMA, MVT::f32, Expand);
227 setOperationAction(ISD::FMA, MVT::f64, Expand);
/freebsd-12-stable/sys/cddl/dev/dtrace/x86/
H A Ddis_tables.c244 FMA, /* FMA instructions, all VEX_RMrX */ enumerator in enum:__anon9863
1550 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1551 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1552 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,1
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h355 /// FMA - Perform a * b + c with no intermediate rounding step.
356 FMA, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h1284 ISDs.push_back(ISD::FMA);
1287 ISDs.push_back(ISD::FMA);
1507 // If we can't lower fmuladd into an FMA estimate the cost as a floating
/freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp3141 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); local
3142 Rep = Builder.CreateCall(FMA, Ops);
3144 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), local
3147 Rep = Builder.CreateCall(FMA, { A, B, C });
3201 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), local
3204 Rep = Builder.CreateCall(FMA, { A, B, C });
3220 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, local
3222 Value *Odd = Builder.CreateCall(FMA, Ops);
3224 Value *Even = Builder.CreateCall(FMA, Ops);
3267 Function *FMA local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DInterleavedLoadCombinePass.cpp1184 auto FMA = MSSA.getMemoryAccess(First); local
1187 if (!MSSA.dominates(MADef, FMA))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h935 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
936 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
937 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
938 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
H A DX86ISelLowering.cpp629 // We don't support FMA.
630 setOperationAction(ISD::FMA, MVT::f64, Expand);
631 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 setOperationAction(ISD::FMA, MVT::f128, LibCall);
782 setOperationAction(ISD::FMA, VT, Expand);
1261 setOperationAction(ISD::FMA, VT, Legal);
1462 setOperationAction(ISD::FMA, VT, Legal);
2002 setTargetDAGCombine(ISD::FMA);
20947 // rsqrt estimate with refinement on x86 prior to FMA require
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp256 case ISD::FMA: return "fma";
H A DLegalizeFloatTypes.cpp95 case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
1157 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
2137 case ISD::FMA: // FMA is same as FMAD
H A DDAGCombiner.cpp1580 case ISD::FMA: return visitFMA(N);
11519 /// Try to perform FMA combining on a given FADD node.
11534 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
11552 // Always prefer FMAD to FMA for precision.
11553 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
11737 /// Try to perform FMA combining on a given FSUB node.
11751 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
11770 // Always prefer FMAD to FMA for precision.
11771 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
12037 /// Try to perform FMA combinin
[all...]
H A DLegalizeVectorTypes.cpp146 case ISD::FMA:
941 case ISD::FMA:
2848 case ISD::FMA:
H A DLegalizeVectorOps.cpp437 case ISD::FMA:
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1583 setOperationAction(ISD::FMA, MVT::f64, Expand);
1910 return isOperationLegalOrCustom(ISD::FMA, VT);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp137 setOperationAction(ISD::FMA, MVT::f16, Promote);
392 setOperationAction(ISD::FMA, Ty, Legal);
1903 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1620 setOperationAction(ISD::FMA , MVT::f128, Expand);
1625 setOperationAction(ISD::FMA , MVT::f64, Expand);
1630 setOperationAction(ISD::FMA , MVT::f32, Expand);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp301 setOperationAction(ISD::FMA , MVT::f64, Expand);
302 setOperationAction(ISD::FMA , MVT::f32, Expand);
304 setOperationAction(ISD::FMA , MVT::f64, Legal);
305 setOperationAction(ISD::FMA , MVT::f32, Legal);
755 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
822 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
938 setOperationAction(ISD::FMA, MVT::f128, Legal);
1495 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
8086 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
10015 Value = DAG.getNode(ISD::FMA, d
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp76 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
537 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
4407 // which guarantees that the FMA will not increase register pressure at node N.
4439 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp263 setOperationAction(ISD::FMA, MVT::f128, Expand);
442 setOperationAction(ISD::FMA, MVT::f16, Promote);
470 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
489 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
712 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
8856 /// Not profitable if I and it's user can form a FMA instruction
8878 isOperationLegalOrCustom(ISD::FMA, getValueType(DL, Ty)) &&

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