Searched refs:ExtVal (Results 1 - 14 of 14) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 74 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | WebAssemblyISelLowering.cpp | 567 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
570 MVT ExtT = ExtVal.getSimpleValueType();
571 MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 1978 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); local
1979 if (!ExtVal || !ExtVal->hasOneUse() ||
1980 ExtVal->getParent() == CI->getParent())
1983 ExtVal->moveBefore(CI);
1986 InsertedInsts.insert(ExtVal);
3974 Value *ExtVal = SExt; local
3984 ExtVal = ZExt;
3997 Instruction *ExtInst = dyn_cast<Instruction>(ExtVal);
4004 return ExtVal;
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 799 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | AArch64ISelLowering.cpp | 3064 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
3065 return ExtVal.getValueType().isScalableVector();
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 362 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
| H A D | ARMISelLowering.cpp | 15016 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
15017 EVT VT = ExtVal.getValueType();
15022 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal.getOperand(0))) {
15031 if (ExtVal->use_empty() ||
15032 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
15035 SDNode *U = *ExtVal->use_begin();
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2385 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, local
2388 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2389 Ops.push_back(ExtVal);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2179 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); local
2185 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2200 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2492 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2494 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1733 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, local
1736 return ExtVal;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 4149 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() local
4151 Ops.push_back(DAG.getTargetConstant(Offset + ExtVal,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4858 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | [all...] |
Completed in 727 milliseconds