Searched refs:AR_PHY_65NM_CH0_RXTX2 (Results 1 - 4 of 4) sorted by relevance

/freebsd-12-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_tx99_tgt.c171 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
193 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
288 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
353 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
423 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
[all...]
H A Dar9300_misc.c3452 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3453 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3477 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3478 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3585 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3586 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3662 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3663 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3745 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3746 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
[all...]
H A Dar9300_reset.c3049 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3050 OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3052 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3060 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3061 OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */
3064 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
[all...]
H A Dar9300phy.h913 #define AR_PHY_65NM_CH0_RXTX2 AR_PHY_65NM(ch0_RXTX2) macro

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