Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (Results 1 - 2 of 2) sorted by relevance

/freebsd-11.0-release/sys/arm/xilinx/
H A Dzy7_slcr.c366 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
416 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
H A Dzy7_slcr.h154 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (0x3f << 8) macro

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