1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/11.0/sys/arm/xilinx/zy7_slcr.c 299069 2016-05-04 15:48:59Z pfg $
27 */
28
29/*
30 * Zynq-700 SLCR driver.  Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012.  Xilinx doc UG585.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: releng/11.0/sys/arm/xilinx/zy7_slcr.c 299069 2016-05-04 15:48:59Z pfg $");
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/lock.h>
46#include <sys/mutex.h>
47#include <sys/resource.h>
48#include <sys/sysctl.h>
49#include <sys/rman.h>
50
51#include <machine/bus.h>
52#include <machine/resource.h>
53#include <machine/stdarg.h>
54
55#include <dev/fdt/fdt_common.h>
56#include <dev/ofw/ofw_bus.h>
57#include <dev/ofw/ofw_bus_subr.h>
58
59#include <arm/xilinx/zy7_slcr.h>
60
61struct zy7_slcr_softc {
62	device_t	dev;
63	struct mtx	sc_mtx;
64	struct resource	*mem_res;
65};
66
67static struct zy7_slcr_softc *zy7_slcr_softc_p;
68extern void (*zynq7_cpu_reset);
69
70#define ZSLCR_LOCK(sc)		mtx_lock(&(sc)->sc_mtx)
71#define	ZSLCR_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
72#define ZSLCR_LOCK_INIT(sc) \
73	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev),	\
74	    "zy7_slcr", MTX_DEF)
75#define ZSLCR_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx);
76
77#define RD4(sc, off) 		(bus_read_4((sc)->mem_res, (off)))
78#define WR4(sc, off, val) 	(bus_write_4((sc)->mem_res, (off), (val)))
79
80#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY	33333333	/* 33.3 Mhz */
81
82SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
83
84static char zynq_bootmode[64];
85SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
86	      "Zynq boot mode");
87
88static char zynq_pssid[100];
89SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
90	   "Zynq PSS IDCODE");
91
92static uint32_t zynq_reboot_status;
93SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
94	   0, "Zynq REBOOT_STATUS register");
95
96static int ps_clk_frequency;
97SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
98	   0, "Zynq PS_CLK Frequency");
99
100static int io_pll_frequency;
101SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
102	   0, "Zynq IO PLL Frequency");
103
104static int arm_pll_frequency;
105SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
106	   &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
107
108static int ddr_pll_frequency;
109SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
110	   &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
111
112static void
113zy7_slcr_unlock(struct zy7_slcr_softc *sc)
114{
115
116	/* Unlock SLCR with magic number. */
117	WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
118}
119
120static void
121zy7_slcr_lock(struct zy7_slcr_softc *sc)
122{
123
124	/* Lock SLCR with magic number. */
125	WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
126}
127
128static void
129zy7_slcr_cpu_reset(void)
130{
131	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
132
133	/* Unlock SLCR registers. */
134	zy7_slcr_unlock(sc);
135
136	/* This has something to do with a work-around so the fsbl will load
137	 * the bitstream after soft-reboot.  It's very important.
138	 */
139	WR4(sc, ZY7_SLCR_REBOOT_STAT,
140	    RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
141
142	/* Soft reset */
143	WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
144
145	for (;;)
146		;
147}
148
149/* Assert PL resets and disable level shifters in preparation of programming
150 * the PL (FPGA) section.  Called from zy7_devcfg.c.
151 */
152void
153zy7_slcr_preload_pl(void)
154{
155	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
156
157	if (!sc)
158		return;
159
160	ZSLCR_LOCK(sc);
161
162	/* Unlock SLCR registers. */
163	zy7_slcr_unlock(sc);
164
165	/* Assert top level output resets. */
166	WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
167
168	/* Disable all level shifters. */
169	WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
170
171	/* Lock SLCR registers. */
172	zy7_slcr_lock(sc);
173
174	ZSLCR_UNLOCK(sc);
175}
176
177/* After PL configuration, enable level shifters and deassert top-level
178 * PL resets.  Called from zy7_devcfg.c.  Optionally, the level shifters
179 * can be left disabled but that's rare of an FPGA application. That option
180 * is controlled by a sysctl in the devcfg driver.
181 */
182void
183zy7_slcr_postload_pl(int en_level_shifters)
184{
185	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
186
187	if (!sc)
188		return;
189
190	ZSLCR_LOCK(sc);
191
192	/* Unlock SLCR registers. */
193	zy7_slcr_unlock(sc);
194
195	if (en_level_shifters)
196		/* Enable level shifters. */
197		WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
198
199	/* Deassert top level output resets. */
200	WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
201
202	/* Lock SLCR registers. */
203	zy7_slcr_lock(sc);
204
205	ZSLCR_UNLOCK(sc);
206}
207
208/* Override cgem_set_refclk() in gigabit ethernet driver
209 * (sys/dev/cadence/if_cgem.c).  This function is called to
210 * request a change in the gem's reference clock speed.
211 */
212int
213cgem_set_ref_clk(int unit, int frequency)
214{
215	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
216	int div0, div1;
217
218	if (!sc)
219		return (-1);
220
221	/* Find suitable divisor pairs.  Round result to nearest khz
222	 * to test for match.
223	 */
224	for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
225		div0 = (io_pll_frequency + div1 * frequency / 2) /
226			div1 / frequency;
227		if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
228		    ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
229		    (frequency + 500) / 1000)
230			break;
231	}
232
233	if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
234		return (-1);
235
236	ZSLCR_LOCK(sc);
237
238	/* Unlock SLCR registers. */
239	zy7_slcr_unlock(sc);
240
241	/* Modify GEM reference clock. */
242	WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
243	    (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
244	    (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
245	    ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
246	    ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
247
248	/* Lock SLCR registers. */
249	zy7_slcr_lock(sc);
250
251	ZSLCR_UNLOCK(sc);
252
253	return (0);
254}
255
256/*
257 * PL clocks management function
258 */
259int
260zy7_pl_fclk_set_source(int unit, int source)
261{
262	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
263	uint32_t reg;
264
265	if (!sc)
266		return (-1);
267
268	ZSLCR_LOCK(sc);
269
270	/* Unlock SLCR registers. */
271	zy7_slcr_unlock(sc);
272
273	/* Modify FPGAx source. */
274	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
275	reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
276	reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
277	WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
278
279	/* Lock SLCR registers. */
280	zy7_slcr_lock(sc);
281
282	ZSLCR_UNLOCK(sc);
283
284	return (0);
285}
286
287int
288zy7_pl_fclk_get_source(int unit)
289{
290	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
291	uint32_t reg;
292	int source;
293
294	if (!sc)
295		return (-1);
296
297	ZSLCR_LOCK(sc);
298
299	/* Modify GEM reference clock. */
300	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
301	source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>
302	    ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT;
303
304	/* ZY7_PL_FCLK_SRC_IO is actually b0x */
305	if ((source & 2) == 0)
306		source = ZY7_PL_FCLK_SRC_IO;
307
308	ZSLCR_UNLOCK(sc);
309
310	return (source);
311}
312
313int
314zy7_pl_fclk_set_freq(int unit, int frequency)
315{
316	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
317	int div0, div1;
318	int base_frequency;
319	uint32_t reg;
320	int source;
321
322	if (!sc)
323		return (-1);
324
325	source = zy7_pl_fclk_get_source(unit);
326	switch (source) {
327		case ZY7_PL_FCLK_SRC_IO:
328			base_frequency = io_pll_frequency;
329			break;
330
331		case ZY7_PL_FCLK_SRC_ARM:
332			base_frequency = arm_pll_frequency;
333			break;
334
335		case ZY7_PL_FCLK_SRC_DDR:
336			base_frequency = ddr_pll_frequency;
337			break;
338
339		default:
340			return (-1);
341	}
342
343	/* Find suitable divisor pairs.  Round result to nearest khz
344	 * to test for match.
345	 */
346	for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
347		div0 = (base_frequency + div1 * frequency / 2) /
348			div1 / frequency;
349		if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
350		    ((base_frequency / div0 / div1) + 500) / 1000 ==
351		    (frequency + 500) / 1000)
352			break;
353	}
354
355	if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
356		return (-1);
357
358	ZSLCR_LOCK(sc);
359
360	/* Unlock SLCR registers. */
361	zy7_slcr_unlock(sc);
362
363	/* Modify FPGAx reference clock. */
364	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
365	reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
366	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
367	reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
368	    (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
369	WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
370
371	/* Lock SLCR registers. */
372	zy7_slcr_lock(sc);
373
374	ZSLCR_UNLOCK(sc);
375
376	return (base_frequency / div0 / div1);
377}
378
379int
380zy7_pl_fclk_get_freq(int unit)
381{
382	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
383	int div0, div1;
384	int base_frequency;
385	int frequency;
386	uint32_t reg;
387	int source;
388
389	if (!sc)
390		return (-1);
391
392	source = zy7_pl_fclk_get_source(unit);
393	switch (source) {
394		case ZY7_PL_FCLK_SRC_IO:
395			base_frequency = io_pll_frequency;
396			break;
397
398		case ZY7_PL_FCLK_SRC_ARM:
399			base_frequency = arm_pll_frequency;
400			break;
401
402		case ZY7_PL_FCLK_SRC_DDR:
403			base_frequency = ddr_pll_frequency;
404			break;
405
406		default:
407			return (-1);
408	}
409
410	ZSLCR_LOCK(sc);
411
412	/* Modify FPGAx reference clock. */
413	reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
414	div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
415	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;
416	div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
417	    ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT;
418
419	ZSLCR_UNLOCK(sc);
420
421	if (div0 == 0)
422		div0 = 1;
423
424	if (div1 == 0)
425		div1 = 1;
426
427	frequency = (base_frequency / div0 / div1);
428	/* Round to KHz */
429	frequency = (frequency + 500) / 1000;
430	frequency = frequency * 1000;
431
432	return (frequency);
433}
434
435int
436zy7_pl_fclk_enable(int unit)
437{
438	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
439
440	if (!sc)
441		return (-1);
442
443	ZSLCR_LOCK(sc);
444
445	/* Unlock SLCR registers. */
446	zy7_slcr_unlock(sc);
447
448	WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
449	WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
450
451	/* Lock SLCR registers. */
452	zy7_slcr_lock(sc);
453
454	ZSLCR_UNLOCK(sc);
455
456	return (0);
457}
458
459int
460zy7_pl_fclk_disable(int unit)
461{
462	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
463
464	if (!sc)
465		return (-1);
466
467	ZSLCR_LOCK(sc);
468
469	/* Unlock SLCR registers. */
470	zy7_slcr_unlock(sc);
471
472	WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
473	WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
474
475	/* Lock SLCR registers. */
476	zy7_slcr_lock(sc);
477
478	ZSLCR_UNLOCK(sc);
479
480	return (0);
481}
482
483int
484zy7_pl_fclk_enabled(int unit)
485{
486	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
487	uint32_t reg;
488
489	if (!sc)
490		return (-1);
491
492	ZSLCR_LOCK(sc);
493	reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
494	ZSLCR_UNLOCK(sc);
495
496	return !(reg & 1);
497}
498
499int
500zy7_pl_level_shifters_enabled()
501{
502	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
503
504	uint32_t reg;
505
506	if (!sc)
507		return (-1);
508
509	ZSLCR_LOCK(sc);
510	reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
511	ZSLCR_UNLOCK(sc);
512
513	return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);
514}
515
516void
517zy7_pl_level_shifters_enable()
518{
519	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
520
521	if (!sc)
522		return;
523
524	ZSLCR_LOCK(sc);
525	zy7_slcr_unlock(sc);
526	WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
527	zy7_slcr_lock(sc);
528	ZSLCR_UNLOCK(sc);
529}
530
531void
532zy7_pl_level_shifters_disable()
533{
534	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
535
536	if (!sc)
537		return;
538
539	ZSLCR_LOCK(sc);
540	zy7_slcr_unlock(sc);
541	WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
542	zy7_slcr_lock(sc);
543	ZSLCR_UNLOCK(sc);
544}
545
546static int
547zy7_slcr_probe(device_t dev)
548{
549
550	if (!ofw_bus_status_okay(dev))
551		return (ENXIO);
552
553	if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
554		return (ENXIO);
555
556	device_set_desc(dev, "Zynq-7000 slcr block");
557	return (0);
558}
559
560static int
561zy7_slcr_attach(device_t dev)
562{
563	struct zy7_slcr_softc *sc = device_get_softc(dev);
564	int rid;
565	phandle_t node;
566	pcell_t cell;
567	uint32_t bootmode;
568	uint32_t pss_idcode;
569	uint32_t arm_pll_ctrl;
570	uint32_t ddr_pll_ctrl;
571	uint32_t io_pll_ctrl;
572	static char *bootdev_names[] = {
573		"JTAG", "Quad-SPI", "NOR", "(3?)",
574		"NAND", "SD Card", "(6?)", "(7?)"
575	};
576
577	/* Allow only one attach. */
578	if (zy7_slcr_softc_p != NULL)
579		return (ENXIO);
580
581	sc->dev = dev;
582
583	ZSLCR_LOCK_INIT(sc);
584
585	/* Get memory resource. */
586	rid = 0;
587	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
588					     RF_ACTIVE);
589	if (sc->mem_res == NULL) {
590		device_printf(dev, "could not allocate memory resources.\n");
591		return (ENOMEM);
592	}
593
594	/* Hook up cpu_reset. */
595	zy7_slcr_softc_p = sc;
596	zynq7_cpu_reset = zy7_slcr_cpu_reset;
597
598	/* Read info and set sysctls. */
599	bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
600	snprintf(zynq_bootmode, sizeof(zynq_bootmode),
601		 "0x%x: boot device: %s", bootmode,
602		 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
603
604	pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
605	snprintf(zynq_pssid, sizeof(zynq_pssid),
606		 "0x%x: manufacturer: 0x%x device: 0x%x "
607		 "family: 0x%x sub-family: 0x%x rev: 0x%x",
608		 pss_idcode,
609		 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
610		 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
611		 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
612		 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
613		 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
614		 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
615		 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
616		 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
617		 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
618		 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
619
620	zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
621
622	/* Derive PLL frequencies from PS_CLK. */
623	node = ofw_bus_get_node(dev);
624	if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
625		ps_clk_frequency = fdt32_to_cpu(cell);
626	else
627		ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
628
629	arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
630	ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
631	io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
632
633	/* Determine ARM PLL frequency. */
634	if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
635	     (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
636	    ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
637	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
638		/* PLL is bypassed. */
639		arm_pll_frequency = ps_clk_frequency;
640	else
641		arm_pll_frequency = ps_clk_frequency *
642			((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
643			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
644
645	/* Determine DDR PLL frequency. */
646	if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
647	     (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
648	    ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
649	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
650		/* PLL is bypassed. */
651		ddr_pll_frequency = ps_clk_frequency;
652	else
653		ddr_pll_frequency = ps_clk_frequency *
654			((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
655			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
656
657	/* Determine IO PLL frequency. */
658	if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
659	     (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
660	    ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
661	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
662		/* PLL is bypassed. */
663		io_pll_frequency = ps_clk_frequency;
664	else
665		io_pll_frequency = ps_clk_frequency *
666			((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
667			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
668
669	/* Lock SLCR registers. */
670	zy7_slcr_lock(sc);
671
672	return (0);
673}
674
675static int
676zy7_slcr_detach(device_t dev)
677{
678	struct zy7_slcr_softc *sc = device_get_softc(dev);
679
680	bus_generic_detach(dev);
681
682	/* Release memory resource. */
683	if (sc->mem_res != NULL)
684		bus_release_resource(dev, SYS_RES_MEMORY,
685			     rman_get_rid(sc->mem_res), sc->mem_res);
686
687	zy7_slcr_softc_p = NULL;
688	zynq7_cpu_reset = NULL;
689
690	ZSLCR_LOCK_DESTROY(sc);
691
692	return (0);
693}
694
695static device_method_t zy7_slcr_methods[] = {
696	/* device_if */
697	DEVMETHOD(device_probe, 	zy7_slcr_probe),
698	DEVMETHOD(device_attach, 	zy7_slcr_attach),
699	DEVMETHOD(device_detach, 	zy7_slcr_detach),
700
701	DEVMETHOD_END
702};
703
704static driver_t zy7_slcr_driver = {
705	"zy7_slcr",
706	zy7_slcr_methods,
707	sizeof(struct zy7_slcr_softc),
708};
709static devclass_t zy7_slcr_devclass;
710
711DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
712MODULE_VERSION(zy7_slcr, 1);
713