/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 155 return MI.getDesc().TSFlags & SIInstrFlags::SALU; 159 return get(Opcode).TSFlags & SIInstrFlags::SALU; 163 return MI.getDesc().TSFlags & SIInstrFlags::VALU; 167 return get(Opcode).TSFlags & SIInstrFlags::VALU; 171 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; 175 return get(Opcode).TSFlags & SIInstrFlags::SOP1; 179 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; 183 return get(Opcode).TSFlags & SIInstrFlags::SOP2; 187 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; 191 return get(Opcode).TSFlags [all...] |
H A D | R600Defines.h | 62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST) 63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
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H A D | SIInsertWaits.cpp | 149 uint64_t TSFlags = MI.getDesc().TSFlags; local 152 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT); 155 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT && 159 if (TSFlags & SIInstrFlags::LGKM_CNT) {
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H A D | R600OptimizeVectorRegisters.cpp | 134 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 250 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
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H A D | AMDGPUInstrInfo.cpp | 257 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE; 261 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
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H A D | R600InstrInfo.cpp | 39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; 43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; 132 unsigned TargetFlags = get(Opcode).TSFlags; 138 unsigned TargetFlags = get(Opcode).TSFlags; 146 unsigned TargetFlags = get(Opcode).TSFlags; 198 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT); 1339 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0; 1344 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; 1399 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; 1420 unsigned TargetFlags = get(MI->getOpcode()).TSFlags; [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 185 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && 190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; 209 /// in an instruction with the specified TSFlags. 210 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 211 unsigned Size = X86II::getSizeOfImm(TSFlags); 212 bool isPCRel = X86II::isImmPCRel(TSFlags); 362 EmitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 587 EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const argument 988 DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, const MCInstrDesc &Desc) argument 1108 EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, const MCSubtargetInfo &STI, raw_ostream &OS) const argument 1167 uint64_t TSFlags = Desc.TSFlags; local [all...] |
H A D | X86BaseInfo.h | 575 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { argument 576 return TSFlags >> X86II::OpcodeShift; 579 inline bool hasImm(uint64_t TSFlags) { argument 580 return (TSFlags & X86II::ImmMask) != 0; 583 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 585 inline unsigned getSizeOfImm(uint64_t TSFlags) { argument 586 switch (TSFlags & X86II::ImmMask) { 600 /// TSFlags indicates that it is pc relative. 601 inline unsigned isImmPCRel(uint64_t TSFlags) { argument 602 switch (TSFlags 619 isImmSigned(uint64_t TSFlags) argument 670 getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXReplaceImageHandles.cpp | 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { 89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { 95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { 97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); 105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { 112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
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H A D | NVPTXInstrInfo.cpp | 69 // Look for the appropriate part of TSFlags 72 unsigned TSFlags = local 73 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; 74 isMove = (TSFlags == 1); 93 unsigned TSFlags = local 94 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; 95 isLoad = (TSFlags == 1); 104 unsigned TSFlags = local 105 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift; 106 isStore = (TSFlags [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { 55 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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H A D | MLxExpansionPass.cpp | 188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 169 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 177 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 184 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 195 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 213 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 219 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 227 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 242 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 260 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 266 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/InstPrinter/ |
H A D | WebAssemblyInstPrinter.cpp | 100 : (Desc.TSFlags & WebAssemblyII::VariableOpImmediateIsLabel))) 134 MII.get(MI->getOpcode()).TSFlags == 0) && 135 "WebAssembly variable_ops register ops don't use TSFlags"); 150 (MII.get(MI->getOpcode()).TSFlags & 154 // TODO: (MII.get(MI->getOpcode()).TSFlags & 161 MII.get(MI->getOpcode()).TSFlags == 0) && 162 "WebAssembly variable_ops floating point ops don't use TSFlags"); 166 (MII.get(MI->getOpcode()).TSFlags &
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 135 ((Desc.TSFlags & R600_InstFlag::OP1) || 136 Desc.TSFlags & R600_InstFlag::OP2)) { 170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 287 uint64_t TSFlags = MCID.TSFlags; local 289 isFirst = TSFlags & PPCII::PPC970_First; 290 isSingle = TSFlags & PPCII::PPC970_Single; 291 isCracked = TSFlags & PPCII::PPC970_Cracked; 292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.cpp | 44 uint64_t TSFlags = Desc.TSFlags; local 51 if (TSFlags & X86II::LOCK)
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H A D | X86IntelInstPrinter.cpp | 39 uint64_t TSFlags = Desc.TSFlags; local 41 if (TSFlags & X86II::LOCK)
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 144 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, MI.getOpcode()) + 242 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, MI.getOpcode()); 338 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, Opcode); 431 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, MI.getOpcode()) +
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 1039 const uint64_t F = MI->getDesc().TSFlags; 1456 const uint64_t F = MI->getDesc().TSFlags; 1651 const uint64_t F = MI->getDesc().TSFlags; 1821 const uint64_t F = MID.TSFlags; 1843 const uint64_t F = MI->getDesc().TSFlags; 1859 const uint64_t F = get(Opcode).TSFlags; 2080 const uint64_t F = MI->getDesc().TSFlags; 2086 const uint64_t F = get(Opcode).TSFlags; 2107 const uint64_t F = MI->getDesc().TSFlags; 2113 const uint64_t F = get(Opcode).TSFlags; [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 244 unsigned MIFlags = Desc.TSFlags; 250 unsigned CompareFlags = Compare->getDesc().TSFlags; 266 unsigned Flags = MI->getDesc().TSFlags;
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H A D | SystemZRegisterInfo.cpp | 105 if (MI->getDesc().TSFlags & SystemZII::HasIndex
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H A D | SystemZInstrInfo.cpp | 202 if ((MCID.TSFlags & Flag) && 494 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0; 625 return ((MCID.TSFlags & Flag) && 872 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags); 881 if (MemDesc.TSFlags & SystemZII::HasIndex) 1159 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); 1177 if (MCID.TSFlags & SystemZII::Has20BitOffset)
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/Disassembler/ |
H A D | WebAssemblyDisassembler.cpp | 134 if (Desc.TSFlags & WebAssemblyII::VariableOpIsImmediate) {
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/freebsd-11.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 146 uint64_t TSFlags; // Target Specific Flag values member in class:llvm::MCInstrDesc
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