| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1086 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1140 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1149 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1158 Rt == Rt2)
1169 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1228 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1241 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1252 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1263 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1274 DecodeFPR32RegisterClass(Inst, Rt2, Add
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1623 unsigned Rt2 = Rt + 1; local
1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1651 if (Rt2 == 15)
1670 if (Rt2 == 15)
1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1680 if (writeback && (Rn == Rt || Rn == Rt2))
4859 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
4864 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Addres
4885 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
4932 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
4969 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5027 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); local
5205 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 648 uint32_t Rt2 = Bits32(opcode, 14, 10); local
654 integer t2 = UInt(Rt2);
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 3477 // the Rt == Rt2. All of those are undefined behaviour.
3485 unsigned Rt2 = Inst.getOperand(2).getReg(); local
3490 if (RI->isSubRegisterEq(Rn, Rt2))
3502 unsigned Rt2 = Inst.getOperand(1).getReg(); local
3503 if (Rt == Rt2)
3504 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3515 unsigned Rt2 = Inst.getOperand(2).getReg(); local
3516 if (Rt == Rt2)
3517 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3531 unsigned Rt2 local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5903 unsigned Rt2 = MRI->getEncodingValue(Reg2); local
5905 // Rt2 must be Rt + 1 and Rt must be even.
5906 if (Rt + 1 != Rt2 || (Rt & 1)) {
6099 // Rt2 must be Rt + 1.
6100 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6101 if (Rt2 != Rt + 1)
6109 if (Rn == Rt || Rn == Rt2)
6120 // Rt2 must be different from Rt.
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6123 if (Rt2
6139 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6149 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 10240 //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32);
10516 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32);
10753 uint32_t Rt2 = ReadCoreReg (t2, &success);
10761 if (!MemAWrite (context, address + 4, Rt2, addr_byte_size))
12599 { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
12600 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12621 { 0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
12622 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12919 { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
12946 { 0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<R
[all...] |