Searched refs:Rt (Results 1 - 19 of 19) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp316 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
320 MCOperand &Rt = Inst.getOperand(3); local
321 assert (Rt.isReg() && "Expected register and none was found");
322 unsigned Reg = RI->getEncodingValue(Rt.getReg());
327 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
331 MCOperand &Rt = Inst.getOperand(2); local
332 assert (Rt.isReg() && "Expected register and none was found");
333 unsigned Reg = RI->getEncodingValue(Rt.getReg());
338 Rt
343 MCOperand &Rt = Inst.getOperand(2); local
537 MCOperand &Rt = Inst.getOperand(1); local
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H A DHexagonBitTracker.cpp223 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
226 assert(Ws == Rt.width());
227 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
230 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
H A DHexagonBitSimplify.cpp546 case S2_storerf_io: // memh(Rs32+#s11:1)=Rt.H32
547 case S2_pstorerft_io: // if (Pv4) memh(Rs32+#u6:1)=Rt.H32
548 case S2_pstorerff_io: // if (!Pv4) memh(Rs32+#u6:1)=Rt.H32
549 case S4_pstorerftnew_io: // if (Pv4.new) memh(Rs32+#u6:1)=Rt.H32
550 case S4_pstorerffnew_io: // if (!Pv4.new) memh(Rs32+#u6:1)=Rt.H32
551 case S2_storerf_pi: // memh(Rx32++#s4:1)=Rt.H32
552 case S2_pstorerft_pi: // if (Pv4) memh(Rx32++#s4:1)=Rt.H32
553 case S2_pstorerff_pi: // if (!Pv4) memh(Rx32++#s4:1)=Rt.H32
554 case S2_pstorerftnew_pi: // if (Pv4.new) memh(Rx32++#s4:1)=Rt.H32
555 case S2_pstorerffnew_pi: // if (!Pv4.new) memh(Rx32++#s4:1)=Rt
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H A DHexagonInstrInfo.cpp963 unsigned Rt = Op3.getReg(); local
970 .addReg(Pu, (Rd == Rt) ? K1 : 0)
972 if (Rd != Rt)
975 .addReg(Rt, K3);
3291 // memw(Rs+#u4:2) = Rt
3292 // memb(Rs+#u4:0) = Rt
3295 // memw(r29+#u5:2) = Rt
3303 // memw(Rs+#u4:2) = Rt
3310 // memb(Rs+#u4:0) = Rt
3320 // memh(Rs+#u3:1) = Rt
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp207 MCOperand Rs, Rt; local
217 Rt = L.getOperand(0);
222 CompoundInsn->addOperand(Rt);
228 Rt = L.getOperand(0);
234 CompoundInsn->addOperand(Rt);
243 Rt = L.getOperand(2);
249 CompoundInsn->addOperand(Rt);
256 Rt = L.getOperand(2);
262 CompoundInsn->addOperand(Rt);
269 Rt
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/freebsd-11.0-release/contrib/ofed/management/infiniband-diags/scripts/
H A Dibprintca.pl118 if ($line =~ /^Switch.*/ || $line =~ /^Rt.*/) { $in_hca = "no"; }
H A Dibprintrt.pl103 if ($line =~ /^Rt.*\"R-(.*)\"\s+# (.*)/) {
H A Dibfindnodesusing.pl190 if ($line =~ /^Ca.*/ || $line =~ /^Rt.*/) { $in_switch = "no"; }
H A Dibidsverify.pl213 if ($line =~ /^Rt.*/) {
H A DIBswcountlimits.pm408 if ($line =~ /^Ca.*/ || $line =~ /^Rt.*/) { $in_switch = "no"; }
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp838 unsigned Rt = fieldFromInstruction(insn, 0, 5); local
848 // Rt is an immediate in prefetch.
849 Inst.addOperand(MCOperand::createImm(Rt));
859 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
866 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
870 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
874 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
878 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
882 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
886 DecodeFPR8RegisterClass(Inst, Rt, Add
899 unsigned Rt = fieldFromInstruction(insn, 0, 5); local
1084 unsigned Rt = fieldFromInstruction(insn, 0, 5); local
1167 unsigned Rt = fieldFromInstruction(insn, 0, 5); local
1537 uint64_t Rt = fieldFromInstruction(insn, 0, 5); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp565 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
569 if (Rs >= Rt) {
572 } else if (Rs != 0 && Rs < Rt) {
583 Rt)));
604 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
608 if (Rs >= Rt) {
611 } else if (Rs != 0 && Rs < Rt) {
622 Rt)));
644 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
648 if (Rt
689 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
731 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
780 InsnType Rt = fieldFromInstruction(insn, 16, 5); local
1641 unsigned Rt = fieldFromInstruction(Insn, 16, 5); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1466 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
1474 // On stores, the writeback operand precedes Rt.
1491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1494 // On loads, the writeback operand comes after Rt.
1525 if (writeback && (Rn == 15 || Rn == Rt))
1614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
1623 unsigned Rt2 = Rt + 1;
1627 // For {LD,ST}RD, Rt must be even, else undefined.
1635 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1647 if (writeback && (Rn == 15 || Rn == Rt || R
3306 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
3389 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
3473 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
3553 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
3591 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
3747 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4159 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4181 unsigned Rt = fieldFromInstruction(Insn, 0, 4); local
4206 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4231 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4259 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4284 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4858 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4884 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4931 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
4968 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
5026 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local
5174 unsigned Rt = fieldFromInstruction(Val, 12, 4); local
5204 unsigned Rt = fieldFromInstruction(Val, 12, 4); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1573 MCOperand &Rt = Inst.getOperand(1); local
1576 TmpInst.addOperand(Rt);
1577 TmpInst.addOperand(Rt);
1612 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
2026 MCOperand &Rt = Inst.getOperand(2); local
2027 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2033 Rt.setReg(MatchRegisterName(RegPair));
2039 Rt.setReg(MatchRegisterName(RegPair));
2048 MCOperand &Rt = Inst.getOperand(3); local
2049 unsigned int RegNum = RI->getEncodingValue(Rt
2073 MCOperand &Rt = Inst.getOperand(2); local
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/freebsd-11.0-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp650 uint32_t Rt = Bits32(opcode, 4, 0); local
653 integer t = UInt(Rt);
1082 integer t = UInt(Rt);
1121 integer t = UInt(Rt);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2799 unsigned Rt = MI->getOperand(0).getReg(); local
2801 return (Rt == Rm) ? 4 : 3;
2806 unsigned Rt = MI->getOperand(0).getReg(); local
2808 if (Rt == Rm)
2836 unsigned Rt = MI->getOperand(0).getReg(); local
2840 if (Rt == Rm)
2849 unsigned Rt = MI->getOperand(0).getReg(); local
2851 return (Rt == Rm) ? 3 : 2;
2872 unsigned Rt = MI->getOperand(0).getReg(); local
2873 if (Rt
2887 unsigned Rt = MI->getOperand(0).getReg(); local
2911 unsigned Rt = MI->getOperand(0).getReg(); local
2920 unsigned Rt = MI->getOperand(0).getReg(); local
2956 unsigned Rt = MI->getOperand(0).getReg(); local
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/freebsd-11.0-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp399 uint32_t Rt; // the source register local
418 Rt = Bits32(opcode, 15, 12);
420 if (BadReg(Rt))
422 registers = (1u << Rt);
431 Rt = Bits32(opcode, 15, 12);
433 if (Rt == dwarf_sp)
435 registers = (1u << Rt);
518 uint32_t Rt; // the destination register local
540 Rt = Bits32(opcode, 15, 12);
542 if (Rt
1249 uint32_t Rt; // the destination register local
3961 uint32_t Rt; // the destination register local
5300 uint32_t Rt = ReadCoreReg (t, &success); local
9978 uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); local
10072 uint32_t Rt = ReadCoreReg (t, &success); local
10175 uint32_t Rt = ReadCoreReg (t, &success); local
10734 uint32_t Rt = ReadCoreReg (t, &success); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3477 // the Rt == Rt2. All of those are undefined behaviour.
3484 unsigned Rt = Inst.getOperand(1).getReg(); local
3487 if (RI->isSubRegisterEq(Rn, Rt))
3501 unsigned Rt = Inst.getOperand(0).getReg(); local
3503 if (Rt == Rt2)
3504 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3514 unsigned Rt = Inst.getOperand(1).getReg(); local
3516 if (Rt == Rt2)
3517 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
3530 unsigned Rt local
3563 unsigned Rt = Inst.getOperand(1).getReg(); local
3582 unsigned Rt = Inst.getOperand(1).getReg(); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5902 unsigned Rt = MRI->getEncodingValue(Reg1); local
5905 // Rt2 must be Rt + 1 and Rt must be even.
5906 if (Rt + 1 != Rt2 || (Rt & 1)) {
6088 // Rt can't be R14.
6091 "Rt can't be R14");
6093 const unsigned Rt = MRI->getEncodingValue(RtReg); local
6094 // Rt must be even-numbered.
6095 if ((Rt
6121 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local
6138 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local
6148 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6166 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local
6189 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local
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