Searched refs:REG_WR (Results 1 - 8 of 8) sorted by relevance

/freebsd-11.0-release/sys/dev/bxe/
H A Decore_init_ops.h54 REG_WR(sc, addr + i*4, data[i]);
284 REG_WR(sc, addr, op->write.val);
526 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
527 REG_WR(sc, read_arb_addr[i].add,
529 REG_WR(sc, read_arb_addr[i].ubound,
537 REG_WR(sc, write_arb_addr[i].l,
540 REG_WR(sc, write_arb_addr[i].add,
543 REG_WR(sc, write_arb_addr[i].ubound,
548 REG_WR(sc, write_arb_addr[i].l,
552 REG_WR(s
[all...]
H A Dbxe.c1002 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1046 REG_WR(sc, hw_lock_control_reg, resource_bit);
1091 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1127 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1160 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1172 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1190 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1193 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1197 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1303 REG_WR(s
[all...]
H A Dbxe_elink.c956 REG_WR(sc, reg, val);
965 REG_WR(sc, reg, val);
993 REG_WR(sc, params->lfa_base +
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1200 REG_WR(s
[all...]
H A Decore_init.h274 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
279 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
284 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
295 REG_WR(sc, reg_addr, reg_bit_map);
644 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
646 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
649 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
650 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
757 REG_WR(s
[all...]
H A Dbxe.h1903 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) macro
1959 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1967 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1973 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
2293 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2363 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2390 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
H A Decore_sp.c920 REG_WR(sc, (ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
3595 REG_WR(sc, ECORE_MC_HASH_OFFSET(sc, i), mc_filter[i]);
/freebsd-11.0-release/sys/dev/bce/
H A Dif_bce.c1678 REG_WR(sc, offset, val);
1798 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1814 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1850 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1851 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1866 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1867 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1903 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1913 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1942 REG_WR(s
[all...]
H A Dif_bcereg.h1087 #define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val) macro
1091 #define REG_WR(sc, offset, val) \ macro
1105 REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1107 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

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