Lines Matching refs:REG_WR
1678 REG_WR(sc, offset, val);
1798 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1814 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1850 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1851 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1866 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1867 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1903 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1913 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1942 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1986 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1995 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
2015 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2105 REG_WR(sc, BCE_EMAC_MODE, val);
2157 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2197 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2235 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2240 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2241 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2279 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2305 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2330 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2367 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2368 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2369 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2426 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2427 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2428 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2492 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2495 REG_WR(sc, BCE_NVM_WRITE, val32);
2496 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2497 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2593 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2594 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2595 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2596 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
4031 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4033 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4038 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4042 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4048 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4051 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4777 REG_WR(sc, BCE_CTX_COMMAND, val);
4795 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4798 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4800 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4833 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4834 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4840 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4841 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4914 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4919 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4945 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4993 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
5005 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5025 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5037 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5085 REG_WR(sc, BCE_EMAC_MODE, val);
5131 REG_WR(sc, BCE_DMA_CONFIG, val);
5134 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5149 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5168 REG_WR(sc, BCE_MQ_CONFIG, val);
5171 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5172 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5176 REG_WR(sc, BCE_RV2P_CONFIG, val);
5182 REG_WR(sc, BCE_TBDR_CONFIG, val);
5215 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5221 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5224 REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5226 REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5230 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5232 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5241 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5244 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5247 REG_WR(sc, BCE_HC_TX_TICKS,
5249 REG_WR(sc, BCE_HC_RX_TICKS,
5251 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5252 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5254 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5255 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5256 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5268 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5270 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5273 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5277 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5296 REG_WR(sc, BCE_HC_CONFIG, val);
5299 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5323 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5331 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5340 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5345 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5348 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5796 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5914 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
6010 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6467 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6472 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6502 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
7037 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7055 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7059 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7064 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7147 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7151 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7209 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7549 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7907 REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7961 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7988 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
8108 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8127 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8138 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8142 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8143 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8144 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8703 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
9692 REG_WR(sc, BCE_MISC_COMMAND, val);
9709 REG_WR(sc, BCE_MISC_COMMAND, val);
10304 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10310 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10316 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10322 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10477 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);