Searched refs:PPC (Results 1 - 25 of 44) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp1 //===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
21 case PPC::PRED_EQ: return PPC::PRED_NE;
22 case PPC::PRED_NE: return PPC::PRED_EQ;
23 case PPC::PRED_LT: return PPC
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H A DPPCFixupKinds.h1 //===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
15 #undef PPC macro
18 namespace PPC { namespace in namespace:llvm
H A DPPCAsmBackend.cpp1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
35 case PPC::fixup_ppc_nofixup:
37 case PPC::fixup_ppc_brcond14:
38 case PPC::fixup_ppc_brcond14abs:
40 case PPC::fixup_ppc_br24:
41 case PPC::fixup_ppc_br24abs:
43 case PPC::fixup_ppc_half16:
45 case PPC::fixup_ppc_half16ds:
57 case PPC::fixup_ppc_half16:
58 case PPC
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H A DPPCPredicates.h1 //===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
17 // GCC #defines PPC on Linux but we use it as our namespace name
18 #undef PPC macro
20 // Generated files will use "namespace PPC". To avoid symbol clash,
21 // undefine PPC here. PPC may be predefined on some hosts.
22 #undef PPC macro
25 namespace PPC { namespace in namespace:llvm
H A DPPCMCCodeEmitter.cpp1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
161 (MCFixupKind)PPC::fixup_ppc_br24));
173 (MCFixupKind)PPC::fixup_ppc_brcond14));
186 (MCFixupKind)PPC::fixup_ppc_br24abs));
199 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
211 (MCFixupKind)PPC::fixup_ppc_half16));
229 (MCFixupKind)PPC::fixup_ppc_half16));
248 (MCFixupKind)PPC::fixup_ppc_half16ds));
311 (MCFixupKind)PPC::fixup_ppc_nofixup));
314 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC
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H A DPPCELFObjectWriter.cpp1 //===-- PPCELFObjectWriter.cpp - PPC ELF Writer ---------------------------===//
80 case PPC::fixup_ppc_br24:
81 case PPC::fixup_ppc_br24abs:
95 case PPC::fixup_ppc_brcond14:
96 case PPC::fixup_ppc_brcond14abs:
99 case PPC::fixup_ppc_half16:
116 case PPC::fixup_ppc_half16ds:
132 case PPC::fixup_ppc_br24abs:
135 case PPC::fixup_ppc_brcond14abs:
138 case PPC
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp10 #include "PPC.h"
66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
71 PPC
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h18 #include "PPC.h"
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30 Reg = PPC::CR0;
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC
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H A DPPCInstrInfo.cpp16 #include "PPC.h"
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
100 if (Directive != PPC
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H A DPPCRegisterInfo.cpp16 #include "PPC.h"
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC
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H A DPPCTLSDynamicCall.cpp25 #include "PPC.h"
61 if (MI->getOpcode() != PPC::ADDItlsgdLADDR &&
62 MI->getOpcode() != PPC::ADDItlsldLADDR &&
63 MI->getOpcode() != PPC::ADDItlsgdLADDR32 &&
64 MI->getOpcode() != PPC::ADDItlsldLADDR32) {
74 unsigned GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
84 case PPC::ADDItlsgdLADDR:
85 Opc1 = PPC::ADDItlsgdL;
86 Opc2 = PPC
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H A DPPCFrameLowering.cpp1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC
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H A DPPCVSXSwapRemoval.cpp46 #include "PPC.h"
172 return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
173 isRegInClass(Reg, &PPC::VRRCRegClass));
178 return (isRegInClass(Reg, &PPC::VSFRCRegClass) ||
179 isRegInClass(Reg, &PPC::VSSRCRegClass));
286 case PPC::XXPERMDI: {
335 case PPC::LVX:
342 case PPC::LXVD2X:
343 case PPC::LXVW4X:
349 case PPC
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H A DPPCHazardRecognizers.cpp15 #include "PPC.h"
68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
83 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } namespace in namespace:llvm
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC
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H A DPPCFastISel.cpp16 #include "PPC.h"
149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
158 unsigned FP64LoadOpc = PPC::LFD);
212 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
224 return Optional<PPC::Predicate>();
228 return PPC::PRED_EQ;
233 return PPC::PRED_GT;
238 return PPC::PRED_GE;
243 return PPC
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H A DPPCBranchSelector.cpp18 #include "PPC.h"
143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
188 if (I->getOpcode() == PPC::BCC) {
190 // 0. PPC branc
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H A DPPCAsmPrinter.cpp19 #include "PPC.h"
115 return "Linux PPC Assembly Printer";
136 return "Darwin PPC Assembly Printer";
251 break; // PPC never has a prefix.
343 MII->getOpcode() == PPC::DBG_VALUE ||
353 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP));
374 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LI8)
378 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::RLDIC)
383 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORIS8)
388 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC
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H A DPPCISelDAGToDAG.cpp1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
11 // converting from a legalized dag to a PPC dag.
15 #include "PPC.h"
45 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
68 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
259 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
278 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
279 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
289 BuildMI(EntryBB, IP, dl, TII.get(PPC
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H A DPPCVSXCopy.cpp18 #include "PPC.h"
69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
77 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
81 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI);
85 return IsRegInClass(Reg, &PPC::VSSRCRegClass, MRI);
108 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass :
109 &PPC::VSLRCRegClass;
122 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 :
123 PPC
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H A DPPCEarlyReturn.cpp17 #include "PPC.h"
66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
82 if (J->getOpcode() == PPC::B) {
94 } else if (J->getOpcode() == PPC::BCC) {
98 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
108 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
114 TII->get(J->getOpcode() == PPC::BC ? PPC
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H A DPPCSubtarget.cpp1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
15 #include "PPC.h"
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
60 DarwinDirective = PPC::DIR_NONE;
163 case PPC::DIR_440:
164 case PPC::DIR_A2:
165 case PPC::DIR_E500mc:
166 case PPC::DIR_E5500:
167 case PPC
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H A DPPCTOCRegDeps.cpp66 #include "PPC.h"
103 if (MI.getOpcode() == PPC::LDtocL ||
104 MI.getOpcode() == PPC::ADDItocL)
122 MI.addOperand(MachineOperand::CreateReg(PPC::X2,
H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
46 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
49 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
52 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
70 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
129 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
394 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
518 addRegisterClass(MVT::v4f32, &PPC
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.cpp1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
10 // This class prints an PPC MCInst to a .s file.
59 if (MI->getOpcode() == PPC::RLWINM) {
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
92 if (MI->getOpcode() == PPC::RLDICR) {
115 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
118 if (MI->getOpcode() == PPC::DCBTST)
124 bool IsBookE = STI.getFeatureBits()[PPC
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