Searched refs:PACKET3 (Results 1 - 14 of 14) sorted by relevance

/freebsd-11.0-release/sys/dev/drm2/radeon/
H A Devergreen_blit_kms.c59 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
97 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
101 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
117 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
155 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
209 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
237 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
242 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
247 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_RE
[all...]
H A Dr600_blit_kms.c57 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
74 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
78 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
82 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
86 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
105 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_RE
[all...]
H A Dni.c928 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
931 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
937 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
950 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
955 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
961 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
972 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
975 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1031 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1049 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNT
[all...]
H A Dsi.c1803 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1806 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1815 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1833 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1836 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1847 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1854 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1869 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1872 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYN
[all...]
H A Dr600.c2211 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2481 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2568 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2576 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2584 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2591 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2594 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2598 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2618 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3063 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_RE
[all...]
H A Devergreen.c1609 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1614 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1620 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1627 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1681 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1700 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1706 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1710 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
H A Dsid.h809 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
813 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dnid.h502 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
H A Dr300d.h48 /* PACKET3 op code */
67 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Drv515d.h191 /* PACKET3 op code */
207 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Dr100d.h48 /* PACKET3 op code */
66 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Devergreend.h1005 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
H A Dr600d.h1167 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
H A Dr100.c920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
1678 /* FIXME: only allow PACKET3 blit? easier to check for out of
2001 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "

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