160786Sps/* 260786Sps * Copyright 2008 Advanced Micro Devices, Inc. 360786Sps * Copyright 2008 Red Hat Inc. 460786Sps * Copyright 2009 Jerome Glisse. 560786Sps * 660786Sps * Permission is hereby granted, free of charge, to any person obtaining a 760786Sps * copy of this software and associated documentation files (the "Software"), 860786Sps * to deal in the Software without restriction, including without limitation 960786Sps * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1060786Sps * and/or sell copies of the Software, and to permit persons to whom the 1160786Sps * Software is furnished to do so, subject to the following conditions: 1260786Sps * 1360786Sps * The above copyright notice and this permission notice shall be included in 1460786Sps * all copies or substantial portions of the Software. 1560786Sps * 1660786Sps * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1760786Sps * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1860786Sps * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1960786Sps * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2060786Sps * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2160786Sps * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2260786Sps * OTHER DEALINGS IN THE SOFTWARE. 2360786Sps * 2460786Sps * Authors: Dave Airlie 2560786Sps * Alex Deucher 2660786Sps * Jerome Glisse 2760786Sps */ 2860786Sps#ifndef __R300D_H__ 2960786Sps#define __R300D_H__ 3060786Sps 3160786Sps#include <sys/cdefs.h> 3260786Sps__FBSDID("$FreeBSD: releng/11.0/sys/dev/drm2/radeon/r300d.h 254885 2013-08-25 19:37:15Z dumbbell $"); 3360786Sps 3460786Sps#define CP_PACKET0 0x00000000 3560786Sps#define PACKET0_BASE_INDEX_SHIFT 0 3660786Sps#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 3760786Sps#define PACKET0_COUNT_SHIFT 16 3860786Sps#define PACKET0_COUNT_MASK (0x3fff << 16) 3960786Sps#define CP_PACKET1 0x40000000 4060786Sps#define CP_PACKET2 0x80000000 4160786Sps#define PACKET2_PAD_SHIFT 0 4260786Sps#define PACKET2_PAD_MASK (0x3fffffff << 0) 4360786Sps#define CP_PACKET3 0xC0000000 4460786Sps#define PACKET3_IT_OPCODE_SHIFT 8 4560786Sps#define PACKET3_IT_OPCODE_MASK (0xff << 8) 4660786Sps#define PACKET3_COUNT_SHIFT 16 4760786Sps#define PACKET3_COUNT_MASK (0x3fff << 16) 4860786Sps/* PACKET3 op code */ 4960786Sps#define PACKET3_NOP 0x10 5060786Sps#define PACKET3_3D_DRAW_VBUF 0x28 5160786Sps#define PACKET3_3D_DRAW_IMMD 0x29 5260786Sps#define PACKET3_3D_DRAW_INDX 0x2A 5360786Sps#define PACKET3_3D_LOAD_VBPNTR 0x2F 5460786Sps#define PACKET3_3D_CLEAR_ZMASK 0x32 5560786Sps#define PACKET3_INDX_BUFFER 0x33 5660786Sps#define PACKET3_3D_DRAW_VBUF_2 0x34 5760786Sps#define PACKET3_3D_DRAW_IMMD_2 0x35 5860786Sps#define PACKET3_3D_DRAW_INDX_2 0x36 5960786Sps#define PACKET3_3D_CLEAR_HIZ 0x37 6060786Sps#define PACKET3_3D_CLEAR_CMASK 0x38 6160786Sps#define PACKET3_BITBLT_MULTI 0x9B 6260786Sps 6360786Sps#define PACKET0(reg, n) (CP_PACKET0 | \ 6460786Sps REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 6560786Sps REG_SET(PACKET0_COUNT, (n))) 6660786Sps#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 6760786Sps#define PACKET3(op, n) (CP_PACKET3 | \ 6860786Sps REG_SET(PACKET3_IT_OPCODE, (op)) | \ 6960786Sps REG_SET(PACKET3_COUNT, (n))) 7060786Sps 7160786Sps#define PACKET_TYPE0 0 7260786Sps#define PACKET_TYPE1 1 7360786Sps#define PACKET_TYPE2 2 7460786Sps#define PACKET_TYPE3 3 7560786Sps 7660786Sps#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 7760786Sps#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 7860786Sps#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 7960786Sps#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 8060786Sps#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 8160786Sps 8260786Sps/* Registers */ 8360786Sps#define R_000148_MC_FB_LOCATION 0x000148 8460786Sps#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 8560786Sps#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 8660786Sps#define C_000148_MC_FB_START 0xFFFF0000 8760786Sps#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 8860786Sps#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 8960786Sps#define C_000148_MC_FB_TOP 0x0000FFFF 9060786Sps#define R_00014C_MC_AGP_LOCATION 0x00014C 9160786Sps#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 9260786Sps#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 9360786Sps#define C_00014C_MC_AGP_START 0xFFFF0000 9460786Sps#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 9560786Sps#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 9660786Sps#define C_00014C_MC_AGP_TOP 0x0000FFFF 9760786Sps#define R_00015C_AGP_BASE_2 0x00015C 9860786Sps#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 9960786Sps#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 10060786Sps#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0 10160786Sps#define R_000170_AGP_BASE 0x000170 10260786Sps#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 10360786Sps#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 10460786Sps#define C_000170_AGP_BASE_ADDR 0x00000000 10560786Sps#define R_0007C0_CP_STAT 0x0007C0 10660786Sps#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 10760786Sps#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 10860786Sps#define C_0007C0_MRU_BUSY 0xFFFFFFFE 10960786Sps#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 11060786Sps#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 11160786Sps#define C_0007C0_MWU_BUSY 0xFFFFFFFD 11260786Sps#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 11360786Sps#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 11460786Sps#define C_0007C0_RSIU_BUSY 0xFFFFFFFB 11560786Sps#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 11660786Sps#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 11760786Sps#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 11860786Sps#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 11960786Sps#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 12060786Sps#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 12160786Sps#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 12260786Sps#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 12360786Sps#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 12460786Sps#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 12560786Sps#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 12660786Sps#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 12760786Sps#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 12860786Sps#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 12960786Sps#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 13060786Sps#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 13160786Sps#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 13260786Sps#define C_0007C0_CSI_BUSY 0xFFFFDFFF 13360786Sps#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 13460786Sps#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 13560786Sps#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 13660786Sps#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 13760786Sps#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 13860786Sps#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 13960786Sps#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 14063128Sps#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 14163128Sps#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 14260786Sps#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 14360786Sps#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 14460786Sps#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 14560786Sps#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 14660786Sps#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 14760786Sps#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 14860786Sps#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 14960786Sps#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 15060786Sps#define C_0007C0_CP_BUSY 0x7FFFFFFF 15160786Sps#define R_000E40_RBBM_STATUS 0x000E40 15260786Sps#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 15360786Sps#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 15460786Sps#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 15560786Sps#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 15660786Sps#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 15760786Sps#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 15860786Sps#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 15960786Sps#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 16060786Sps#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 16160786Sps#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 16260786Sps#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 16360786Sps#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 16460786Sps#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 16560786Sps#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 16660786Sps#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 16760786Sps#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 16860786Sps#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 16960786Sps#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 17060786Sps#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 17160786Sps#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 17260786Sps#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 17360786Sps#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 17460786Sps#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 17560786Sps#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 17660786Sps#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 17760786Sps#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 17860786Sps#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 17960786Sps#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 18060786Sps#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 18160786Sps#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 18260786Sps#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 18360786Sps#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 18460786Sps#define C_000E40_E2_BUSY 0xFFFDFFFF 18560786Sps#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 18660786Sps#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 18760786Sps#define C_000E40_RB2D_BUSY 0xFFFBFFFF 18863128Sps#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 18963128Sps#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 19063128Sps#define C_000E40_RB3D_BUSY 0xFFF7FFFF 19160786Sps#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 19260786Sps#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 19360786Sps#define C_000E40_VAP_BUSY 0xFFEFFFFF 19460786Sps#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 19560786Sps#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 19660786Sps#define C_000E40_RE_BUSY 0xFFDFFFFF 19760786Sps#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 19860786Sps#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 19960786Sps#define C_000E40_TAM_BUSY 0xFFBFFFFF 20060786Sps#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 20160786Sps#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 20260786Sps#define C_000E40_TDM_BUSY 0xFF7FFFFF 20360786Sps#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 20460786Sps#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 20560786Sps#define C_000E40_PB_BUSY 0xFEFFFFFF 20660786Sps#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 20760786Sps#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 20860786Sps#define C_000E40_TIM_BUSY 0xFDFFFFFF 20960786Sps#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 21060786Sps#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 21160786Sps#define C_000E40_GA_BUSY 0xFBFFFFFF 21260786Sps#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 21360786Sps#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 21460786Sps#define C_000E40_CBA2D_BUSY 0xF7FFFFFF 215#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 216#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 217#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 218#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 219#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 220#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 221#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 222#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 223#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 224#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 225#define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 226#define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 227#define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 228#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 229#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 230#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 231#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 232#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 233#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 234#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 235#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 236#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 237#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 238#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 239#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 240#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 241#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 242#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 243#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 244#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 245#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 246#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 247#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 248#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 249#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 250#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 251#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 252#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 253#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 254#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 255#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 256#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 257#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 258#define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 259#define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 260#define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 261#define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 262#define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 263#define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 264 265#define R_00000D_SCLK_CNTL 0x00000D 266#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 267#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 268#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 269#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) 270#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) 271#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7 272#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) 273#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) 274#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF 275#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) 276#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) 277#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF 278#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) 279#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) 280#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF 281#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) 282#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) 283#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F 284#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8) 285#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1) 286#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF 287#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9) 288#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1) 289#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF 290#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10) 291#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1) 292#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF 293#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11) 294#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1) 295#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF 296#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12) 297#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1) 298#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF 299#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13) 300#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1) 301#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF 302#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14) 303#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1) 304#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF 305#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15) 306#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1) 307#define C_00000D_FORCE_DISP2 0xFFFF7FFF 308#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 309#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 310#define C_00000D_FORCE_CP 0xFFFEFFFF 311#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 312#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 313#define C_00000D_FORCE_HDP 0xFFFDFFFF 314#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18) 315#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1) 316#define C_00000D_FORCE_DISP1 0xFFFBFFFF 317#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 318#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 319#define C_00000D_FORCE_TOP 0xFFF7FFFF 320#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 321#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 322#define C_00000D_FORCE_E2 0xFFEFFFFF 323#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 324#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 325#define C_00000D_FORCE_SE 0xFFDFFFFF 326#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 327#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 328#define C_00000D_FORCE_IDCT 0xFFBFFFFF 329#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 330#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 331#define C_00000D_FORCE_VIP 0xFF7FFFFF 332#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 333#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 334#define C_00000D_FORCE_RE 0xFEFFFFFF 335#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 336#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 337#define C_00000D_FORCE_PB 0xFDFFFFFF 338#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 339#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 340#define C_00000D_FORCE_TAM 0xFBFFFFFF 341#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 342#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 343#define C_00000D_FORCE_TDM 0xF7FFFFFF 344#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 345#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 346#define C_00000D_FORCE_RB 0xEFFFFFFF 347#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) 348#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) 349#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF 350#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) 351#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) 352#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF 353#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) 354#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) 355#define C_00000D_FORCE_OV0 0x7FFFFFFF 356 357#endif 358