Searched refs:NumVecs (Results 1 - 5 of 5) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
216 /// SelectVST - Select NEON store intrinsics. NumVecs should
219 /// For NumVecs <= 2, QOpcodes1 is not used.
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
228 bool isUpdating, unsigned NumVecs,
231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
1688 GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs, bool is64BitVector) argument
1809 SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
1942 SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
2089 SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) argument
2208 SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *Opcodes) argument
2291 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument
[all...]
H A DARMISelLowering.cpp9596 unsigned NumVecs = 0; local
9602 NumVecs = 1; break;
9604 NumVecs = 2; break;
9606 NumVecs = 3; break;
9608 NumVecs = 4; break;
9610 NumVecs = 2; isLaneOp = true; break;
9612 NumVecs = 3; isLaneOp = true; break;
9614 NumVecs = 4; isLaneOp = true; break;
9616 NumVecs = 1; isLoadOp = false; break;
9618 NumVecs
9796 unsigned NumVecs = 0; local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp150 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1018 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, argument
1134 SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1155 SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1187 SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1203 SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1259 SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1299 SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1355 SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1385 SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
[all...]
H A DAArch64ISelLowering.cpp9078 unsigned NumVecs = 0; local
9083 NumVecs = 2; break;
9085 NumVecs = 3; break;
9087 NumVecs = 4; break;
9089 NumVecs = 2; IsStore = true; break;
9091 NumVecs = 3; IsStore = true; break;
9093 NumVecs = 4; IsStore = true; break;
9095 NumVecs = 2; break;
9097 NumVecs = 3; break;
9099 NumVecs
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp[all...]

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