Target/AArch64/AArch64ISelDAGToDAG.cpp

150   SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154   SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156   SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158   SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159   SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161   SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162   SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163   SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164   SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1018 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,
1028                                N->op_begin() + Vec0Off + NumVecs);
1035   Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1134 SDNode *AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs,
1147   for (unsigned i = 0; i < NumVecs; ++i)
1151   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1155 SDNode *AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1171   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1175   if (NumVecs == 1)
1178     for (unsigned i = 0; i < NumVecs; ++i)
1183   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1187 SDNode *AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1194   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1197   SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1203 SDNode *AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1212   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1216                    N->getOperand(NumVecs + 1), // base register
1217                    N->getOperand(NumVecs + 2), // Incremental
1259 SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1266   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1277       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1280                    N->getOperand(NumVecs + 3), N->getOperand(0)};
1287   for (unsigned i = 0; i < NumVecs; ++i) {
1294   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1299 SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1306   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1318       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1323                    N->getOperand(NumVecs + 2),                  // Base register
1324                    N->getOperand(NumVecs + 3),                  // Incremental
1329   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1333   if (NumVecs == 1) {
1340     for (unsigned i = 0; i < NumVecs; ++i) {
1350   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1355 SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1362   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1371       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1374                    N->getOperand(NumVecs + 3), N->getOperand(0)};
1385 SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1392   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1404       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1407                    N->getOperand(NumVecs + 2), // Base Register
1408                    N->getOperand(NumVecs + 3), // Incremental