Searched refs:N2 (Results 1 - 24 of 24) sorted by relevance

/freebsd-11.0-release/contrib/llvm/include/llvm/ADT/
H A DStringSwitch.h102 template<unsigned N0, unsigned N1, unsigned N2>
105 const char (&S2)[N2], const T& Value) {
109 (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0))) {
116 template<unsigned N0, unsigned N1, unsigned N2, unsigned N3>
119 const char (&S2)[N2], const char (&S3)[N3],
124 (N2-1 == Str.size() && std::memcmp(S2, Str.data(), N2-1) == 0) ||
132 template<unsigned N0, unsigned N1, unsigned N2, unsigned N3, unsigned N4>
135 const char (&S2)[N2], cons
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/freebsd-11.0-release/share/examples/netgraph/
H A Dvirtual.chain232 M4=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
234 M5=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
236 M6=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
H A Dvirtual.lan225 M4=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
227 M5=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
229 M6=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
/freebsd-11.0-release/crypto/openssl/crypto/bn/asm/
H A Darmv4-mont.pl250 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
311 vmlal.u32 $A4xB,$Ni,${N2}[0]
313 vmlal.u32 $A5xB,$Ni,${N2}[1]
359 vmlal.u32 $A4xB,$Ni,${N2}[0]
361 vmlal.u32 $A5xB,$Ni,${N2}[1]
398 vmlal.u32 $A4xB,$Ni,${N2}[0]
400 vmlal.u32 $A5xB,$Ni,${N2}[1]
407 vld1.32 {$N2-$N3}, [$nptr]!
430 vmlal.u32 $A4xB,$Ni,${N2}[0]
432 vmlal.u32 $A5xB,$Ni,${N2}[
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H A Dppc64-mont.pl165 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
392 lfd $N2,`$FRAME+112`($sp)
400 fcfid $N2,$N2
419 stfd $N2,56($nap_d) ; save n[j+1] in double format
433 fmadd $T2a,$N2,$na,$T2a
434 fmadd $T2b,$N2,$nb,$T2b
444 fmadd $T3a,$N2,$nc,$T3a
445 fmadd $T3b,$N2,$nd,$T3b
531 lfd $N2,`
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp86 /// instructions are specified through \p N1 and \p N2. The address
89 const MachineInstr &MI2, unsigned N2,
276 const MachineInstr &MI2, unsigned N2,
282 if (!isIdenticalOp(MI1.getOperand(N1 + N), MI2.getOperand(N2 + N)))
287 const MachineOperand *Op2 = &MI2.getOperand(N2 + X86::AddrDisp);
275 isSimilarMemOp(const MachineInstr &MI1, unsigned N1, const MachineInstr &MI2, unsigned N2, int64_t &AddrDispShift) argument
H A DX86ISelLowering.cpp11905 SDValue N2 = Op.getOperand(2);
11906 if (!isa<ConstantSDNode>(N2))
11908 auto *N2C = cast<ConstantSDNode>(N2);
11923 N2 = DAG.getIntPtrConstant(1, dl);
11924 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11959 if (N2.getValueType() != MVT::i32)
11960 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11961 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11983 N2 = DAG.getIntPtrConstant(1, dl);
11985 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp929 SDValue N2,
938 Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, *Flags);
944 BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
1479 // commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
1480 // the shuffle mask M that point at N1 to point at N2, and indices that point
1481 // N2 to point at N1.
1482 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { argument
1483 std::swap(N1, N2);
1488 SDValue N2, const int *Mask) {
1489 assert(VT == N1.getValueType() && VT == N2
927 GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1, SDValue N2, const SDNodeFlags *Flags) argument
1487 getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *Mask) argument
1908 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl) argument
3429 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags *Flags) argument
3904 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument
4005 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
4012 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
5606 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2) argument
5612 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) argument
5618 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
5625 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
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H A DDAGCombiner.cpp335 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
336 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
744 SDValue N0, N1, N2; local
745 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
5017 SDValue N2 = N->getOperand(2); local
5022 if (N1 == N2)
5027 return !N0C->isNullValue() ? N1 : N2;
5031 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
5047 isNullConstant(N1) && isOneConstant(N2)) {
5066 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
5571 SDValue N2 = N->getOperand(2); local
5659 SDValue N2 = N->getOperand(2); local
8483 SDValue N2 = N->getOperand(2); local
9316 SDValue N2 = N->getOperand(2); local
13598 SDValue N2 = N->getOperand(2); local
13786 SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2) argument
13970 SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) argument
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H A DInstrEmitter.cpp531 SDValue N2 = Node->getOperand(2);
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
H A DTargetLowering.cpp2091 SDValue N2 = N->getOperand(1); local
2093 if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
2097 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
H A DLegalizeDAG.cpp106 SDValue N1, SDValue N2,
218 SDValue N1, SDValue N2,
227 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
241 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
217 ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, SDValue N1, SDValue N2, ArrayRef<int> Mask) const argument
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h576 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
578 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, argument
582 return getVectorShuffle(VT, dl, N1, N2, MaskElts.data());
683 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
685 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
687 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
689 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
697 SDValue N2);
699 SDValue N2, SDValue N3);
701 SDValue N2, SDValu
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H A DSelectionDAGNodes.h1388 SDValue N2, const int *M)
1390 InitOperands(Ops, N1, N2);
1387 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1, SDValue N2, const int *M) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCommonGEP.cpp68 bool operator()(const GepNode *N1, const GepNode *N2) const {
69 auto F1 = Map.find(N1), F2 = Map.find(N2);
462 NodePair node_pair(GepNode *N1, GepNode *N2) { argument
463 uintptr_t P1 = uintptr_t(N1), P2 = uintptr_t(N2);
465 return std::make_pair(N1, N2);
466 return std::make_pair(N2, N1);
477 bool node_eq(GepNode *N1, GepNode *N2, NodePairSet &Eq, NodePairSet &Ne) { argument
480 if (node_hash(N1) != node_hash(N2))
483 NodePair NP = node_pair(N1, N2);
492 bool Root2 = N2
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp116 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
352 SDValue N1, SDValue N2,
365 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
351 SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8, unsigned Opc16) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1667 SDValue N2 = N->getOperand(2); local
1674 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1679 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1691 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1694 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1704 SDValue N2 = N->getOperand(2); local
1714 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1716 SDValue Borrow = N2;
1718 DAG.getConstant(0, dl, VT), N2);
1730 DAG.computeKnownBits(N2, KnownZer
1743 SDValue N2 = N->getOperand(2); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp2101 SDValue N2 = N->getOperand(2); local
2107 if (SelectDirectAddr(N2, Addr)) {
2135 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2136 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2164 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2165 : SelectADDRri(N2.getNode(), N2, Bas
2321 SDValue N2; local
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/freebsd-11.0-release/contrib/ntp/ntpd/
H A Drefclock_wwv.c439 #define N2 (N15 / 2) /* space (-1) */ macro
442 {N2, N2, 0, 0}, /* 0 */
443 {P2, N2, 0, 0}, /* 1 */
444 {N2, P2, 0, 0}, /* 2 */
/freebsd-11.0-release/contrib/llvm/lib/Analysis/
H A DDependenceAnalysis.cpp1962 // 0 <= i <= N1 and some 0 <= j <= N2, where N1 and N2 are the (normalized)
1973 // a1*0 - a2*N2 <= c2 - c1 <= a1*N1 - a2*0
1974 // -a2*N2 <= c2 - c1 <= a1*N1
1977 // a1*0 - a2*0 <= c2 - c1 <= a1*N1 - a2*N2
1978 // 0 <= c2 - c1 <= a1*N1 - a2*N2
1981 // a1*N1 - a2*N2 <= c2 - c1 <= a1*0 - a2*0
1982 // a1*N1 - a2*N2 <= c2 - c1 <= 0
1985 // a1*N1 - a2*0 <= c2 - c1 <= a1*0 - a2*N2
1986 // a1*N1 <= c2 - c1 <= -a2*N2
2003 const SCEV *N2 = collectUpperBound(Loop2, A1->getType()); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4516 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4519 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4528 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1); local
4529 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4572 /// N2 =+[k1 k3 k0 k2 ]
4588 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1); local
4591 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4595 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
6545 SDValue N2; local
6557 N2
6589 SDValue N2, N3; local
6625 SDValue N2, N3; local
8350 SDValue N2 = N->getOperand(2); local
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H A DARMISelDAGToDAG.cpp2639 SDValue N2 = N0.getOperand(1); local
2640 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2753 SDValue N2 = N->getOperand(2); local
2757 assert(N2.getOpcode() == ISD::Constant);
2761 cast<ConstantSDNode>(N2)->getZExtValue()), dl,
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp950 // (add (add N2, N3), C1) -> addr64
951 SDValue N2 = N0.getOperand(0); local
954 Ptr = N2;
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp2347 TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i+1]; local
2348 assert(N1->getNumTypes() == 1 && N2->getNumTypes() == 1 &&
2351 MadeChange |= N1->UpdateNodeType(0, N2->getExtType(0), *this);
2352 MadeChange |= N2->UpdateNodeType(0, N1->getExtType(0), *this);

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