Searched refs:Mask2 (Results 1 - 5 of 5) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 686 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); local
687 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, LHSKnownZero,
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| /freebsd-11.0-release/contrib/llvm/lib/Transforms/Vectorize/ |
| H A D | BBVectorize.cpp | 2836 std::vector<Constant *> Mask1(numElemI), Mask2(numElemI);
2839 Mask2[v] = ConstantInt::get(Type::getInt32Ty(Context), numElemJ + v);
2851 std::vector<Constant *> Mask1(numElemJ), Mask2(numElemJ);
2854 Mask2[v] = ConstantInt::get(Type::getInt32Ty(Context), numElemI + v);
2858 ConstantVector::get(Mask2),
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1191 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1254 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1298 .addReg(OldVal).addReg(Mask2);
1429 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1499 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1528 .addReg(OldVal).addReg(Mask2);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4125 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); local
4129 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4138 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
9069 unsigned Mask2 = N11C->getZExtValue(); local
9071 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
9074 (Mask == ~Mask2)) {
9081 unsigned amt = countTrailingZeros(Mask2);
9090 (~Mask == Mask2)) {
9094 (Mask2 == 0xffff || Mask2
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| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 3701 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3716 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3721 SmallVector<int,4> Mask2; local
3730 Mask2.push_back(M0);
3742 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3750 if (TLI.isShuffleMaskLegal(Mask2, VT))
3752 N0->getOperand(0), &Mask2[0]);
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