Searched refs:LR (Results 1 - 25 of 89) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DLiveRangeCalc.h80 LiveRange &LR; member in struct:llvm::LiveRangeCalc::LiveInBlock
94 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) argument
95 : LR(LR), DomNode(node), Kill(kill), Value(nullptr) {}
104 /// Assuming that @p LR is live-in to @p UseMBB, find the set of defs that can
108 /// are added to @p LR, and the function returns true.
110 /// If multiple values can reach @p UseMBB, the blocks that need @p LR to be
114 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
128 /// Extend the live range of @p LR to reach all uses of Reg.
132 void extendToUses(LiveRange &LR, unsigne
183 extendToUses(LiveRange &LR, unsigned PhysReg) argument
225 addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill = SlotIndex()) argument
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H A DLiveInterval.cpp52 LiveRange *LR; member in class:__anon2471::CalcLiveRangeUtilBase
55 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} argument
66 VNInfo *VNI = LR->getNextValue(Def, VNInfoAllocator);
86 VNInfo *VNI = LR->getNextValue(Def, VNInfoAllocator);
239 CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {} argument
244 LiveRange::Segments &segmentsColl() { return LR->segments; }
246 void insertAtEnd(const Segment &S) { LR
267 CalcLiveRangeUtilSet(LiveRange *LR) argument
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H A DLiveRangeCalc.cpp44 LiveRange &LR, const MachineOperand &MO) {
49 // Create the def in LR. This may find an existing def.
50 LR.createDeadDef(DefIdx, Alloc);
131 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { argument
135 // LR.createDeadDef() will deduplicate.
137 createDeadDef(*Indexes, *Alloc, LR, MO);
141 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, argument
192 extend(LR, UseIdx, Reg);
216 Updater.setDest(&I.LR);
223 void LiveRangeCalc::extend(LiveRange &LR, SlotInde argument
43 createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, LiveRange &LR, const MachineOperand &MO) argument
258 findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use, unsigned PhysReg) argument
438 LiveRange &LR = I.LR; local
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H A DLiveIntervalAnalysis.cpp159 if (LiveRange *LR = RegUnitRanges[i])
160 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
269 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { argument
282 LRCalc->createDeadDefs(LR, *Supers);
286 // Now extend LR to reach all uses.
293 LRCalc->extendToUses(LR, Reg);
299 LR.flushSegmentSet();
329 LiveRange *LR = RegUnitRanges[Unit]; local
330 if (!LR) {
332 LR
352 createSegmentsForValues(LiveRange &LR, iterator_range<LiveInterval::vni_iterator> VNIs) argument
364 extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, ShrinkToUsesWorkList &WorkList, const LiveRange &OldRange) argument
597 extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) argument
605 pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl<SlotIndex> *EndPoints) argument
1001 updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) argument
1043 handleMoveDown(LiveRange &LR) argument
1131 handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) argument
1284 repairOldRegInRange(const MachineBasicBlock::iterator Begin, const MachineBasicBlock::iterator End, const SlotIndex endIdx, LiveRange &LR, const unsigned Reg, LaneBitmask LaneMask) argument
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H A DMachineVerifier.cpp216 void report_context(const LiveRange &LR, unsigned Reg,
442 void MachineVerifier::report_context(const LiveRange &LR, unsigned Reg, argument
447 errs() << "- liverange: " << LR << '\n';
1056 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1057 LiveQueryResult LRQ = LR->Query(UseIdx);
1061 << ' ' << *LR << '\n';
1065 errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1422 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1423 verifyLiveRange(*LR, i);
1426 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR, argument
1518 verifyLiveRangeSegment(const LiveRange &LR, const LiveRange::const_iterator I, unsigned Reg, LaneBitmask LaneMask) argument
1700 verifyLiveRange(const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) argument
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H A DRegAllocFast.cpp233 void RAFast::addKillFlag(const LiveReg &LR) { argument
234 if (!LR.LastUse) return;
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
237 if (MO.getReg() == LR.PhysReg)
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
277 LiveReg &LR local
498 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument
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H A DRegisterCoalescer.cpp1031 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1032 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1056 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1057 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1542 LiveRange &LR = LIS->getRegUnit(*UI); local
1543 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
1627 LiveRange &LR; member in class:__anon2518::JoinVals
1758 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
1761 /// Multiple values in Other.LR can be affected since partial redefinitions
1780 /// Determine if ValNo is a copy of a value number in LR o
1789 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin, bool TrackSubRegLiveness) argument
2367 << Def << ": " << LR << '\\n'); local
2445 DEBUG(dbgs() << "\\t\\tremoved " << i << '@' << Def << ": " << LR << '\\n'); local
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H A DInterferenceCache.cpp226 LiveRange *LR = RegUnits[i].Fixed; local
227 if (I == LR->end() || I->start >= Stop)
229 I = LR->advanceTo(I, Stop);
230 bool Backup = I == LR->end() || I->start >= Stop;
H A DRegisterPressure.cpp392 const LiveRange *LR = getLiveRange(LIS, Reg); local
393 if (LR != nullptr) {
394 LiveQueryResult LRQ = LR->Query(SlotIdx);
528 const LiveRange *LR = getLiveRange(*LIS, Reg); local
529 if (LR) {
530 LiveQueryResult LRQ = LR->Query(SlotIdx);
615 const LiveRange *LR = getLiveRange(*LIS, Reg); local
616 lastUse = LR && LR->Query(SlotIdx).isKill();
926 const LiveRange *LR local
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
H A DPointerArithChecker.cpp44 const MemRegion *LR = LV.getAsRegion(); local
46 if (!LR || !RV.isConstant())
51 if (isa<VarRegion>(LR) || isa<CodeTextRegion>(LR) ||
52 isa<CompoundLiteralRegion>(LR)) {
H A DPointerSubChecker.cpp47 const MemRegion *LR = LV.getAsRegion(); local
50 if (!(LR && RR))
53 const MemRegion *BaseLR = LR->getBaseRegion();
/freebsd-11.0-release/sys/arm/include/
H A Dstack.h55 #define LR 14 macro
/freebsd-11.0-release/contrib/llvm/include/llvm/ExecutionEngine/Orc/
H A DLambdaResolver.h54 typedef LambdaResolver<ExternalLookupFtorT, DylibLookupFtorT> LR; typedef
55 return make_unique<LR>(std::move(ExternalLookupFtor),
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DLiveIntervalAnalysis.h175 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
178 /// If @p LR has a live value at @p Kill, prune its live range by removing
185 void pruneValue(LiveRange &LR, SlotIndex Kill,
222 bool isLiveInToMBB(const LiveRange &LR, argument
224 return LR.liveAt(getMBBStartIdx(mbb));
227 bool isLiveOutOfMBB(const LiveRange &LR, argument
229 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
376 LiveRange *LR = RegUnitRanges[Unit]; local
377 if (!LR) {
380 RegUnitRanges[Unit] = LR
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H A DLivePhysRegs.h140 inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) { argument
141 LR.print(OS);
H A DLiveInterval.h587 inline raw_ostream &operator<<(raw_ostream &OS, const LiveRange &LR) {
588 LR.print(OS);
786 LiveRange *LR;
794 /// Create a LiveRangeUpdater for adding segments to LR.
795 /// LR will temporarily be in an invalid state until flush() is called.
796 LiveRangeUpdater(LiveRange *lr = nullptr) : LR(lr) {}
800 /// Add a segment to LR and coalesce when possible, just like
801 /// LR.addSegment(). Segments should be added in increasing start order for
809 /// Return true if the LR is currently in an invalid state, and flush()
813 /// Flush the updater state to LR s
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/freebsd-11.0-release/sys/arm/arm/
H A Ddb_trace.c84 state->registers[LR]);
85 db_printsym(state->registers[LR], DB_STGY_PROC);
92 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC));
164 state.registers[LR] = ctx->pcb_regs.sf_lr;
184 state.registers[LR] = (uint32_t)__builtin_return_address(0);
/freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp468 ShuffleOps LR = collectShuffleElements(VecOp, Mask, RHS, IC); local
469 assert(LR.second == nullptr || LR.second == RHS);
471 if (LR.first->getType() != RHS->getType()) {
487 return std::make_pair(LR.first, RHS);
588 ShuffleOps LR = collectShuffleElements(&IE, Mask, nullptr, *this); local
592 if (LR.first != &IE && LR.second != &IE) {
594 if (LR.second == nullptr)
595 LR
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/freebsd-11.0-release/contrib/gcc/config/rs6000/
H A Ddarwin-fpsave.asm48 /* saveFP saves R0 -- assumed to be the callers LR -- to 8/16(R1). */
73 /* restFP restores the caller`s LR from 8/16(R1). Note that the code for
96 /* <OFFSET OF F30 RESTORE> restore callers LR */
/freebsd-11.0-release/contrib/llvm/lib/Support/
H A DScaledNumber.cpp27 uint64_t UL = getU(LHS), LL = getL(LHS), UR = getU(RHS), LR = getL(RHS); local
30 uint64_t P1 = UL * UR, P2 = UL * LR, P3 = LL * UR, P4 = LL * LR;
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp45 InitXCoreMCRegisterInfo(X, XCore::LR);
/freebsd-11.0-release/tools/tools/vt/keymaps/
H A Dconvert-keymap.pl106 grep(s/_squote[LR]?_/'/g, @KEYTOKEN);
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp239 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
495 // Record the location of the stored LR
496 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true); local
498 MCCFIInstruction::createOffset(nullptr, LR, StackGrowth));
729 if (Reg != AArch64::LR)
732 // LR maybe referred to later by an @llvm.returnaddress intrinsic.
733 bool LRLiveIn = MF.getRegInfo().isLiveIn(AArch64::LR);
901 SavedRegs.set(AArch64::LR);
960 assert(((OddReg == AArch64::LR
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp146 XCore::LR));
259 // Allocate space on the stack at the same time as saving LR.
262 MBB.addLiveIn(XCore::LR);
265 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
269 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
274 // If necessary, save LR and FP to the stack, as we EXTSP.
387 // If necessary, restore LR and FP from the stack, as we EXTSP.
434 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
435 "LR & FP are always handled in emitPrologue");
464 assert(Reg != XCore::LR
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/freebsd-11.0-release/contrib/byacc/package/
H A Dbyacc.spec17 specification from a file and generates an LR(1) parser for it. The

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