Searched refs:HexagonII (Results 1 - 16 of 16) sorted by relevance
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCDuplexInfo.cpp | 88 case HexagonII::HSIG_None: 91 case HexagonII::HSIG_L1: 92 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A); 93 case HexagonII::HSIG_L2: 94 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 || 95 Gb == HexagonII::HSIG_A); 96 case HexagonII::HSIG_S1: 97 return (Gb == HexagonII [all...] |
H A D | HexagonShuffler.cpp | 99 (*TUL)[HexagonII::TypeCVI_VA] = 101 (*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); 102 (*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); 103 (*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2); 104 (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); 105 (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); 106 (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); 107 (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1); 108 (*TUL)[HexagonII::TypeCVI_VM_LD] = 110 (*TUL)[HexagonII [all...] |
H A D | HexagonMCInstrInfo.cpp | 136 HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR) 167 HexagonII::MemAccessSize 171 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) & 172 HexagonII::MemAccesSizeMask)); 178 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask); 185 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask); 196 return ((F >> HexagonII [all...] |
H A D | HexagonMCCompound.cpp | 81 // enum HexagonII::CompoundGroup 88 return HexagonII::HCG_None; 106 return HexagonII::HCG_A; 120 return HexagonII::HCG_A; 130 return HexagonII::HCG_A; 140 return HexagonII::HCG_A; 150 return HexagonII::HCG_A; 162 return HexagonII::HCG_B; 170 return HexagonII::HCG_C; 174 return HexagonII [all...] |
H A D | HexagonMCCodeEmitter.cpp | 48 return HexagonII::INST_PARSE_LOOP_END; 55 return HexagonII::INST_PARSE_LOOP_END; 60 return HexagonII::INST_PARSE_DUPLEX; 63 return HexagonII::INST_PARSE_PACKET_END; 64 return HexagonII::INST_PARSE_NOT_END; 113 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { 179 assert(Parse == HexagonII::INST_PARSE_DUPLEX && 260 if (insnType == HexagonII::TypePREFIX) { 342 case HexagonII::MemAccessSize::ByteAccess: 344 case HexagonII [all...] |
H A D | HexagonAsmBackend.cpp | 184 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || 185 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && 187 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
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H A D | HexagonMCInstrInfo.h | 28 namespace HexagonII { namespace in namespace:llvm 93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
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H A D | HexagonBaseInfo.h | 26 /// HexagonII - This namespace holds all of the target specific flags that 29 namespace HexagonII { namespace in namespace:llvm 281 } // End namespace HexagonII.
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H A D | HexagonMCChecker.cpp | 148 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD) 153 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD) 215 NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV); 465 if(llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) == HexagonII::TypeCVI_HIST) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 203 case HexagonII::HSIG_None: 206 case HexagonII::HSIG_L1: 207 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A); 208 case HexagonII::HSIG_L2: 209 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 || 210 Gb == HexagonII::HSIG_A); 211 case HexagonII::HSIG_S1: 212 return (Gb == HexagonII [all...] |
H A D | HexagonMCInstLower.cpp | 46 case HexagonII::MO_PCREL: 49 case HexagonII::MO_GOT: 52 case HexagonII::MO_LO16: 55 case HexagonII::MO_HI16: 58 case HexagonII::MO_GPREL: 92 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
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H A D | HexagonInstrInfo.h | 351 HexagonII::CompoundGroup 363 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
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H A D | HexagonRDFOpt.cpp | 156 if (HII.getAddrMode(MI) != HexagonII::PostInc)
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H A D | HexagonISelLowering.cpp | 1374 unsigned char TF = (RM == Reloc::PIC_) ? HexagonII::MO_PCREL : 0; 1392 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL); 1473 HexagonII::MO_PCREL); 1479 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT); 1497 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL); 1506 HexagonII::MO_PCREL); 2621 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
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H A D | HexagonCopyToCombine.cpp | 141 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 201 if ((Instruction & HexagonII::INST_PARSE_MASK) == 202 HexagonII::INST_PARSE_LOOP_END) { 212 if ((Instruction & HexagonII::INST_PARSE_MASK) == 213 HexagonII::INST_PARSE_DUPLEX) { 222 IClassLow = HexagonII::HSIG_L1; 223 IClassHigh = HexagonII::HSIG_L1; 226 IClassLow = HexagonII::HSIG_L2; 227 IClassHigh = HexagonII::HSIG_L1; 230 IClassLow = HexagonII::HSIG_L2; 231 IClassHigh = HexagonII [all...] |
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