1234285Sdim//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This file contains small standalone helper functions and enum definitions for 11234285Sdim// the Hexagon target useful for the compiler back-end and the MC libraries. 12234285Sdim// As such, it deliberately does not include references to LLVM core 13234285Sdim// code gen types, passes, etc.. 14234285Sdim// 15234285Sdim//===----------------------------------------------------------------------===// 16234285Sdim 17280031Sdim#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 18280031Sdim#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 19234285Sdim 20249423Sdim#include "HexagonMCTargetDesc.h" 21249423Sdim#include "llvm/Support/ErrorHandling.h" 22280031Sdim#include <stdint.h> 23249423Sdim 24234285Sdimnamespace llvm { 25234285Sdim 26234285Sdim/// HexagonII - This namespace holds all of the target specific flags that 27234285Sdim/// instruction info tracks. 28234285Sdim/// 29234285Sdimnamespace HexagonII { 30234285Sdim // *** The code below must match HexagonInstrFormat*.td *** // 31234285Sdim 32239462Sdim // Insn types. 33239462Sdim // *** Must match HexagonInstrFormat*.td *** 34239462Sdim enum Type { 35249423Sdim TypePSEUDO = 0, 36249423Sdim TypeALU32 = 1, 37249423Sdim TypeCR = 2, 38249423Sdim TypeJR = 3, 39249423Sdim TypeJ = 4, 40249423Sdim TypeLD = 5, 41249423Sdim TypeST = 6, 42249423Sdim TypeSYSTEM = 7, 43249423Sdim TypeXTYPE = 8, 44249423Sdim TypeMEMOP = 9, 45249423Sdim TypeNV = 10, 46288943Sdim TypeDUPLEX = 11, 47296417Sdim TypeCOMPOUND = 12, 48296417Sdim TypeCVI_FIRST = 13, 49296417Sdim TypeCVI_VA = TypeCVI_FIRST, 50296417Sdim TypeCVI_VA_DV = 14, 51296417Sdim TypeCVI_VX = 15, 52296417Sdim TypeCVI_VX_DV = 16, 53296417Sdim TypeCVI_VP = 17, 54296417Sdim TypeCVI_VP_VS = 18, 55296417Sdim TypeCVI_VS = 19, 56296417Sdim TypeCVI_VINLANESAT= 20, 57296417Sdim TypeCVI_VM_LD = 21, 58296417Sdim TypeCVI_VM_TMP_LD = 22, 59296417Sdim TypeCVI_VM_CUR_LD = 23, 60296417Sdim TypeCVI_VM_VP_LDU = 24, 61296417Sdim TypeCVI_VM_ST = 25, 62296417Sdim TypeCVI_VM_NEW_ST = 26, 63296417Sdim TypeCVI_VM_STU = 27, 64296417Sdim TypeCVI_HIST = 28, 65296417Sdim TypeCVI_LAST = TypeCVI_HIST, 66249423Sdim TypePREFIX = 30, // Such as extenders. 67249423Sdim TypeENDLOOP = 31 // Such as end of a HW loop. 68239462Sdim }; 69239462Sdim 70249423Sdim enum SubTarget { 71249423Sdim HasV2SubT = 0xf, 72249423Sdim HasV2SubTOnly = 0x1, 73249423Sdim NoV2SubT = 0x0, 74249423Sdim HasV3SubT = 0xe, 75249423Sdim HasV3SubTOnly = 0x2, 76249423Sdim NoV3SubT = 0x1, 77249423Sdim HasV4SubT = 0xc, 78249423Sdim NoV4SubT = 0x3, 79249423Sdim HasV5SubT = 0x8, 80249423Sdim NoV5SubT = 0x7 81249423Sdim }; 82239462Sdim 83249423Sdim enum AddrMode { 84249423Sdim NoAddrMode = 0, // No addressing mode 85249423Sdim Absolute = 1, // Absolute addressing mode 86249423Sdim AbsoluteSet = 2, // Absolute set addressing mode 87249423Sdim BaseImmOffset = 3, // Indirect with offset 88249423Sdim BaseLongOffset = 4, // Indirect with long offset 89261991Sdim BaseRegOffset = 5, // Indirect with register offset 90261991Sdim PostInc = 6 // Post increment addressing mode 91249423Sdim }; 92239462Sdim 93296417Sdim // MemAccessSize is represented as 1+log2(N) where N is size in bits. 94288943Sdim enum class MemAccessSize { 95249423Sdim NoMemAccess = 0, // Not a memory acces instruction. 96249423Sdim ByteAccess = 1, // Byte access instruction (memb). 97249423Sdim HalfWordAccess = 2, // Half word access instruction (memh). 98261991Sdim WordAccess = 3, // Word access instruction (memw). 99296417Sdim DoubleWordAccess = 4, // Double word access instruction (memd) 100296417Sdim // 5, // We do not have a 16 byte vector access. 101296417Sdim Vector64Access = 7, // 64 Byte vector access instruction (vmem). 102296417Sdim Vector128Access = 8 // 128 Byte vector access instruction (vmem). 103249423Sdim }; 104249423Sdim 105234285Sdim // MCInstrDesc TSFlags 106239462Sdim // *** Must match HexagonInstrFormat*.td *** 107234285Sdim enum { 108239462Sdim // This 5-bit field describes the insn type. 109239462Sdim TypePos = 0, 110239462Sdim TypeMask = 0x1f, 111234285Sdim 112239462Sdim // Solo instructions. 113239462Sdim SoloPos = 5, 114239462Sdim SoloMask = 0x1, 115276479Sdim // Packed only with A or X-type instructions. 116276479Sdim SoloAXPos = 6, 117276479Sdim SoloAXMask = 0x1, 118276479Sdim // Only A-type instruction in first slot or nothing. 119276479Sdim SoloAin1Pos = 7, 120276479Sdim SoloAin1Mask = 0x1, 121239462Sdim 122234285Sdim // Predicated instructions. 123276479Sdim PredicatedPos = 8, 124249423Sdim PredicatedMask = 0x1, 125276479Sdim PredicatedFalsePos = 9, 126249423Sdim PredicatedFalseMask = 0x1, 127276479Sdim PredicatedNewPos = 10, 128249423Sdim PredicatedNewMask = 0x1, 129276479Sdim PredicateLatePos = 11, 130276479Sdim PredicateLateMask = 0x1, 131249423Sdim 132249423Sdim // New-Value consumer instructions. 133276479Sdim NewValuePos = 12, 134249423Sdim NewValueMask = 0x1, 135249423Sdim // New-Value producer instructions. 136276479Sdim hasNewValuePos = 13, 137249423Sdim hasNewValueMask = 0x1, 138249423Sdim // Which operand consumes or produces a new value. 139276479Sdim NewValueOpPos = 14, 140249423Sdim NewValueOpMask = 0x7, 141249423Sdim // Stores that can become new-value stores. 142276479Sdim mayNVStorePos = 17, 143249423Sdim mayNVStoreMask = 0x1, 144249423Sdim // New-value store instructions. 145276479Sdim NVStorePos = 18, 146249423Sdim NVStoreMask = 0x1, 147276479Sdim // Loads that can become current-value loads. 148276479Sdim mayCVLoadPos = 19, 149276479Sdim mayCVLoadMask = 0x1, 150276479Sdim // Current-value load instructions. 151276479Sdim CVLoadPos = 20, 152276479Sdim CVLoadMask = 0x1, 153249423Sdim 154249423Sdim // Extendable insns. 155276479Sdim ExtendablePos = 21, 156249423Sdim ExtendableMask = 0x1, 157249423Sdim // Insns must be extended. 158276479Sdim ExtendedPos = 22, 159249423Sdim ExtendedMask = 0x1, 160249423Sdim // Which operand may be extended. 161276479Sdim ExtendableOpPos = 23, 162249423Sdim ExtendableOpMask = 0x7, 163249423Sdim // Signed or unsigned range. 164276479Sdim ExtentSignedPos = 26, 165249423Sdim ExtentSignedMask = 0x1, 166249423Sdim // Number of bits of range before extending operand. 167276479Sdim ExtentBitsPos = 27, 168249423Sdim ExtentBitsMask = 0x1f, 169276479Sdim // Alignment power-of-two before extending operand. 170276479Sdim ExtentAlignPos = 32, 171276479Sdim ExtentAlignMask = 0x3, 172249423Sdim 173249423Sdim // Valid subtargets 174276479Sdim validSubTargetPos = 34, 175249423Sdim validSubTargetMask = 0xf, 176249423Sdim 177249423Sdim // Addressing mode for load/store instructions. 178276479Sdim AddrModePos = 40, 179249423Sdim AddrModeMask = 0x7, 180276479Sdim // Access size for load/store instructions. 181276479Sdim MemAccessSizePos = 43, 182296417Sdim MemAccesSizeMask = 0xf, 183249423Sdim 184276479Sdim // Branch predicted taken. 185276479Sdim TakenPos = 47, 186276479Sdim TakenMask = 0x1, 187276479Sdim 188276479Sdim // Floating-point instructions. 189276479Sdim FPPos = 48, 190296417Sdim FPMask = 0x1, 191296417Sdim 192296417Sdim // New-Value producer-2 instructions. 193296417Sdim hasNewValuePos2 = 50, 194296417Sdim hasNewValueMask2 = 0x1, 195296417Sdim 196296417Sdim // Which operand consumes or produces a new value. 197296417Sdim NewValueOpPos2 = 51, 198296417Sdim NewValueOpMask2 = 0x7, 199296417Sdim 200296417Sdim // Accumulator instructions. 201296417Sdim AccumulatorPos = 54, 202296417Sdim AccumulatorMask = 0x1, 203296417Sdim 204296417Sdim // Complex XU, prevent xu competition by prefering slot3 205296417Sdim PrefersSlot3Pos = 55, 206296417Sdim PrefersSlot3Mask = 0x1, 207234285Sdim }; 208234285Sdim 209234285Sdim // *** The code above must match HexagonInstrFormat*.td *** // 210234285Sdim 211249423Sdim // Hexagon specific MO operand flag mask. 212249423Sdim enum HexagonMOTargetFlagVal { 213249423Sdim //===------------------------------------------------------------------===// 214249423Sdim // Hexagon Specific MachineOperand flags. 215249423Sdim MO_NO_FLAG, 216249423Sdim 217249423Sdim HMOTF_ConstExtended = 1, 218249423Sdim 219249423Sdim /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 220249423Sdim /// Used for computing a global address for PIC compilations 221249423Sdim MO_PCREL, 222249423Sdim 223249423Sdim /// MO_GOT - Indicates a GOT-relative relocation 224249423Sdim MO_GOT, 225249423Sdim 226249423Sdim // Low or high part of a symbol. 227249423Sdim MO_LO16, MO_HI16, 228249423Sdim 229249423Sdim // Offset from the base of the SDA. 230249423Sdim MO_GPREL 231249423Sdim }; 232249423Sdim 233288943Sdim // Hexagon Sub-instruction classes. 234288943Sdim enum SubInstructionGroup { 235288943Sdim HSIG_None = 0, 236288943Sdim HSIG_L1, 237288943Sdim HSIG_L2, 238288943Sdim HSIG_S1, 239288943Sdim HSIG_S2, 240288943Sdim HSIG_A, 241288943Sdim HSIG_Compound 242288943Sdim }; 243288943Sdim 244288943Sdim // Hexagon Compound classes. 245288943Sdim enum CompoundGroup { 246288943Sdim HCG_None = 0, 247288943Sdim HCG_A, 248288943Sdim HCG_B, 249288943Sdim HCG_C 250288943Sdim }; 251288943Sdim 252288943Sdim enum InstParseBits { 253280031Sdim INST_PARSE_MASK = 0x0000c000, 254280031Sdim INST_PARSE_PACKET_END = 0x0000c000, 255280031Sdim INST_PARSE_LOOP_END = 0x00008000, 256280031Sdim INST_PARSE_NOT_END = 0x00004000, 257280031Sdim INST_PARSE_DUPLEX = 0x00000000, 258280031Sdim INST_PARSE_EXTENDER = 0x00000000 259280031Sdim }; 260280031Sdim 261296417Sdim enum InstIClassBits : unsigned { 262296417Sdim INST_ICLASS_MASK = 0xf0000000, 263296417Sdim INST_ICLASS_EXTENDER = 0x00000000, 264296417Sdim INST_ICLASS_J_1 = 0x10000000, 265296417Sdim INST_ICLASS_J_2 = 0x20000000, 266296417Sdim INST_ICLASS_LD_ST_1 = 0x30000000, 267296417Sdim INST_ICLASS_LD_ST_2 = 0x40000000, 268296417Sdim INST_ICLASS_J_3 = 0x50000000, 269296417Sdim INST_ICLASS_CR = 0x60000000, 270296417Sdim INST_ICLASS_ALU32_1 = 0x70000000, 271296417Sdim INST_ICLASS_XTYPE_1 = 0x80000000, 272296417Sdim INST_ICLASS_LD = 0x90000000, 273296417Sdim INST_ICLASS_ST = 0xa0000000, 274296417Sdim INST_ICLASS_ALU32_2 = 0xb0000000, 275296417Sdim INST_ICLASS_XTYPE_2 = 0xc0000000, 276296417Sdim INST_ICLASS_XTYPE_3 = 0xd0000000, 277296417Sdim INST_ICLASS_XTYPE_4 = 0xe0000000, 278296417Sdim INST_ICLASS_ALU32_3 = 0xf0000000 279296417Sdim }; 280296417Sdim 281234285Sdim} // End namespace HexagonII. 282234285Sdim 283234285Sdim} // End namespace llvm. 284234285Sdim 285234285Sdim#endif 286