/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | CallingConvEmitter.cpp | 223 MVT::SimpleValueType DestVT = getValueType(DestTy); local 224 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; 225 if (MVT(DestVT).isFloatingPoint()) { 237 MVT::SimpleValueType DestVT = getValueType(DestTy); local 238 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; 239 if (MVT(DestVT).isFloatingPoint()) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, 130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); 132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); 133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, 135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, 940 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 942 if (SrcVT != MVT::f32 || DestVT != MVT::f64) 1014 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 1016 if (SrcVT != MVT::f64 || DestVT ! 1140 MVT DestVT = VA.getLocVT(); local 1148 MVT DestVT = VA.getLocVT(); local 1517 EVT SrcVT, DestVT; local 1554 MVT DestVT = DestEVT.getSimpleVT(); local 1562 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1581 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1596 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1605 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1627 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1641 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 895 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 897 if (SrcVT != MVT::f32 || DestVT != MVT::f64) 913 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 915 if (SrcVT != MVT::f64 || DestVT != MVT::f32) 1158 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 1162 if (DestVT != MVT::i16 && DestVT != MVT::i8) 1330 MVT DestVT = VA.getLocVT(); local 1332 (DestVT 1342 MVT DestVT = VA.getLocVT(); local 1397 MVT DestVT = VA.getValVT(); local 1643 MVT DestVT = VA.getLocVT(); local 1696 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1768 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 1812 MVT DestVT = DestEVT.getSimpleVT(); local [all...] |
H A D | PPCISelLowering.cpp | 6760 EVT DestVT = MVT::Other) { 6761 if (DestVT == MVT::Other) DestVT = Op.getValueType(); 6762 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 6770 EVT DestVT = MVT::Other) { 6771 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 6772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 6780 SDLoc dl, EVT DestVT = MVT::Other) { 6781 if (DestVT [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt); 2720 MVT DestVT; local 2721 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) 2735 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; 2737 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; 2740 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; 2742 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; 2745 DestVT 2753 MVT DestVT; local 2933 MVT DestVT = VA.getLocVT(); local 2943 MVT DestVT = VA.getLocVT(); local 3749 MVT DestVT = DestEVT.getSimpleVT(); local 3802 emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) argument 4211 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument [all...] |
H A D | AArch64ISelLowering.cpp | 4917 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local 4924 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, 4939 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4945 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4950 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4953 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 4957 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 1746 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local 1750 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 1955 MVT DestVT = VA.getLocVT(); local 1956 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); 1958 ArgVT = DestVT; 1964 MVT DestVT = VA.getLocVT(); local 1965 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZEx 2042 MVT DestVT = RVLocs[0].getValVT(); local 2125 MVT DestVT = VA.getValVT(); local 2575 EVT SrcVT, DestVT; local 2593 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument 2748 MVT DestVT = DestEVT.getSimpleVT(); local [all...] |
H A D | ARMISelLowering.cpp | 5739 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local 5747 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, 5763 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 5769 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 5774 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 5777 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 5780 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl); 141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 1120 EVT DestVT = Node->getValueType(0); 1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { 1147 EVT IDestVT = DestVT.changeTypeToInteger(); 1153 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result); 1945 /// a load from the stack slot to DestVT, extending it if needed. 1949 EVT DestVT, [all...] |
H A D | SelectionDAGBuilder.cpp | 2422 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 2424 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); 2442 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 2444 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); 2556 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 2558 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); 2565 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 2567 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); 2574 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 2576 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, [all...] |
H A D | LegalizeTypes.cpp | 927 EVT DestVT) { 931 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); 936 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), 926 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument
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H A D | LegalizeVectorTypes.cpp | 246 EVT DestVT = N->getValueType(0).getVectorElementType(); local 265 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); 1215 EVT DestVT = N->getValueType(0); local 1217 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); 1234 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
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H A D | LegalizeTypes.h | 172 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1070 MVT DestVT = TLI->getRegisterType(NewVT); local 1071 RegisterVT = DestVT; 1072 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1073 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1460 MVT DestVT = getRegisterType(Context, NewVT); local 1461 RegisterVT = DestVT; 1468 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1469 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 1238 EVT DestVT = ASC->getValueType(0); local 1242 unsigned DestSize = DestVT.getSizeInBits(); 1249 DestVT, 1276 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
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H A D | AMDGPUISelLowering.cpp | 555 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { 562 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; 2345 EVT DestVT = Op.getValueType(); local 2346 if (DestVT == MVT::f64) 2349 if (DestVT == MVT::f32) 2360 EVT DestVT = Op.getValueType(); local 2361 if (DestVT == MVT::f32) 2364 if (DestVT == MVT::f64)
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/freebsd-11.0-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 1385 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1386 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 12903 MVT DestVT = Op.getSimpleValueType(); 12905 if (DestVT.bitsLT(MVT::f64)) 12906 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 12908 if (DestVT.bitsGT(MVT::f64)) 12909 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); [all...] |