Lines Matching refs:DestVT

131   SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1120 EVT DestVT = Node->getValueType(0);
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1147 EVT IDestVT = DestVT.changeTypeToInteger();
1153 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1945 /// a load from the stack slot to DestVT, extending it if needed.
1949 EVT DestVT,
1963 unsigned DestSize = DestVT.getSizeInBits();
1964 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1968 // later than DestVT.
1982 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1986 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2547 EVT DestVT,
2599 if (DestVT == MVT::f64) {
2602 } else if (DestVT.bitsLT(MVT::f64)) {
2603 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2605 } else if (DestVT.bitsGT(MVT::f64)) {
2606 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2618 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2641 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2700 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2733 if (DestVT == MVT::f32)
2740 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2748 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2757 EVT DestVT,
2788 return DAG.getNode(OpToUse, dl, DestVT,
2799 EVT DestVT,
2803 EVT NewOutTy = DestVT;
2834 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);