/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, 81 MO.push_back(MachineOperand::CreateReg(0, false, false,
|
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCTOCRegDeps.cpp | 122 MI.addOperand(MachineOperand::CreateReg(PPC::X2,
|
H A D | PPCInstrInfo.cpp | 501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 512 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 570 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 584 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 1778 MachineOperand::CreateReg(*ImpDefs, true, true)); 1784 MachineOperand::CreateReg(*ImpUses, false, true));
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, 159 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, 199 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, 235 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
|
H A D | HexagonPeephole.cpp | 223 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 230 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
|
H A D | HexagonHardwareLoops.cpp | 1870 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true)); 1881 MachineOperand MO = MachineOperand::CreateReg(PredR, false); 1896 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
|
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 200 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 229 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
|
H A D | Thumb2InstrInfo.cpp | 490 MI.addOperand(MachineOperand::CreateReg(0, false)); 521 MI.addOperand(MachineOperand::CreateReg(0, false));
|
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegStackify.cpp | 74 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK, 80 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
|
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 164 unsigned CreateReg(MVT VT);
|
H A D | MachineOperand.h | 597 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
H A D | MachineInstrBuilder.h | 69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
|
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, 400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
|
H A D | ExpandPostRAPseudos.cpp | 76 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
H A D | MachineInstr.cpp | 636 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); 640 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); 1918 addOperand(MachineOperand::CreateReg(IncomingReg, 1984 addOperand(MachineOperand::CreateReg(Reg, 2021 addOperand(MachineOperand::CreateReg(Reg,
|
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIShrinkInstructions.cpp | 192 return MachineOperand::CreateReg(Orig.getReg(),
|
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); 644 Ops.push_back(MachineOperand::CreateReg( 758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true)); 807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); 813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); 826 Ops.push_back(MachineOperand::CreateReg( 832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true, 1129 Op = MachineOperand::CreateReg(Reg, false); 1145 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
|
H A D | FunctionLoweringInfo.cpp | 343 /// CreateReg - Allocate a single virtual register for the given type. 344 unsigned FunctionLoweringInfo::CreateReg(MVT VT) { function in class:FunctionLoweringInfo 369 unsigned R = CreateReg(RegisterVT);
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 329 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, function in class:__anon2995::SparcOperand 743 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); 804 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
|
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 1640 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { function in class:__anon2707::AArch64Operand 2849 AArch64Operand::CreateReg(Reg, true, S, getLoc(), getContext())); 2898 AArch64Operand::CreateReg(Reg, false, S, getLoc(), getContext())); 3125 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); 3146 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); 3858 Operands[2] = AArch64Operand::CreateReg( 3996 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 4011 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 4027 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 4043 Operands[2] = AArch64Operand::CreateReg(zre [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 1634 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true, 1772 return X86Operand::CreateReg(RegNo, Start, End); 1802 return X86Operand::CreateReg(RegNo, Start, End); 2261 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); 2273 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); 2281 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), 2291 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
|
H A D | X86Operand.h | 475 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, function in struct:llvm::X86Operand
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 582 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, function in struct:__anon2822::HexagonOperand 1146 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1162 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1172 Operands.push_back(HexagonOperand::CreateReg(
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 642 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, function in class:__anon2920::MipsOperand 1162 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser); 1170 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser); 1178 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser); 1186 return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser); 1194 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser); 1202 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser); 1210 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser); 1218 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
|
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/MIRParser/ |
H A D | MIParser.cpp | 750 MachineOperand::CreateReg(*ImpDefs, true, true)); 754 MachineOperand::CreateReg(*ImpUses, false, true)); 941 Dest = MachineOperand::CreateReg(
|