Searched refs:Chan (Results 1 - 5 of 5) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp125 for (unsigned Chan = 0; Chan < 4; ++Chan) {
128 if (Chan < 2)
129 DstReg = MI.getOperand(Chan).getReg();
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
136 if (Chan > 0) {
139 if (Chan >= 2)
141 if (Chan !
[all...]
H A DR600OptimizeVectorRegisters.cpp71 unsigned Chan = Instr->getOperand(i + 1).getImm(); local
73 UndefReg.push_back(Chan);
75 RegToChan[MO.getReg()] = Chan;
170 unsigned Chan) {
172 if (RemapChan[j].first == Chan)
175 llvm_unreachable("Chan wasn't reassigned");
194 unsigned Chan = getReassignedChan(RemapChan, Swizzle); local
200 .addImm(Chan);
201 UpdatedRegToChan[SubReg] = Chan;
203 std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan);
168 getReassignedChan( const std::vector<std::pair<unsigned, unsigned> > &RemapChan, unsigned Chan) argument
[all...]
H A DR600MachineScheduler.cpp441 for (int Chan = 3; Chan > -1; --Chan) {
442 bool isOccupied = OccupedSlotsMask & (1 << Chan);
444 SUnit *SU = AttemptFillSlot(Chan, false);
446 OccupedSlotsMask |= (1 << Chan);
H A DR600EmitClauseMarkers.cpp133 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31; local
134 unsigned KCacheIndex = Index * 4 + Chan;
H A DR600InstrInfo.cpp377 unsigned Chan = RI.getHWRegChan(Reg); local
378 Result.push_back(std::pair<int, unsigned>(Index, Chan));
644 unsigned Chan = RI.getHWRegChan(Src.first->getReg()); local
645 Consts.push_back((Index << 2) | Chan);
1087 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1088 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);

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