1284677Sdim//===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===// 2284677Sdim// 3284677Sdim// The LLVM Compiler Infrastructure 4284677Sdim// 5284677Sdim// This file is distributed under the University of Illinois Open Source 6284677Sdim// License. See LICENSE.TXT for details. 7284677Sdim// 8284677Sdim//===----------------------------------------------------------------------===// 9284677Sdim// 10284677Sdim/// \file 11284677Sdim/// Vector, Reduction, and Cube instructions need to fill the entire instruction 12284677Sdim/// group to work correctly. This pass expands these individual instructions 13284677Sdim/// into several instructions that will completely fill the instruction group. 14284677Sdim// 15284677Sdim//===----------------------------------------------------------------------===// 16284677Sdim 17284677Sdim#include "AMDGPU.h" 18284677Sdim#include "R600Defines.h" 19284677Sdim#include "R600InstrInfo.h" 20284677Sdim#include "R600MachineFunctionInfo.h" 21284677Sdim#include "R600RegisterInfo.h" 22284677Sdim#include "AMDGPUSubtarget.h" 23284677Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 24284677Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 25284677Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 26284677Sdim 27284677Sdimusing namespace llvm; 28284677Sdim 29284677Sdimnamespace { 30284677Sdim 31284677Sdimclass R600ExpandSpecialInstrsPass : public MachineFunctionPass { 32284677Sdim 33284677Sdimprivate: 34284677Sdim static char ID; 35284677Sdim const R600InstrInfo *TII; 36284677Sdim 37284677Sdim void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI, 38284677Sdim unsigned Op); 39284677Sdim 40284677Sdimpublic: 41284677Sdim R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID), 42284677Sdim TII(nullptr) { } 43284677Sdim 44284677Sdim bool runOnMachineFunction(MachineFunction &MF) override; 45284677Sdim 46284677Sdim const char *getPassName() const override { 47284677Sdim return "R600 Expand special instructions pass"; 48284677Sdim } 49284677Sdim}; 50284677Sdim 51284677Sdim} // End anonymous namespace 52284677Sdim 53284677Sdimchar R600ExpandSpecialInstrsPass::ID = 0; 54284677Sdim 55284677SdimFunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) { 56284677Sdim return new R600ExpandSpecialInstrsPass(TM); 57284677Sdim} 58284677Sdim 59284677Sdimvoid R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI, 60284677Sdim const MachineInstr *OldMI, unsigned Op) { 61284677Sdim int OpIdx = TII->getOperandIdx(*OldMI, Op); 62284677Sdim if (OpIdx > -1) { 63284677Sdim uint64_t Val = OldMI->getOperand(OpIdx).getImm(); 64284677Sdim TII->setImmOperand(NewMI, Op, Val); 65284677Sdim } 66284677Sdim} 67284677Sdim 68284677Sdimbool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { 69284677Sdim TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); 70284677Sdim 71284677Sdim const R600RegisterInfo &TRI = TII->getRegisterInfo(); 72284677Sdim 73284677Sdim for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); 74284677Sdim BB != BB_E; ++BB) { 75284677Sdim MachineBasicBlock &MBB = *BB; 76284677Sdim MachineBasicBlock::iterator I = MBB.begin(); 77284677Sdim while (I != MBB.end()) { 78284677Sdim MachineInstr &MI = *I; 79284677Sdim I = std::next(I); 80284677Sdim 81284677Sdim // Expand LDS_*_RET instructions 82284677Sdim if (TII->isLDSRetInstr(MI.getOpcode())) { 83284677Sdim int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 84284677Sdim assert(DstIdx != -1); 85284677Sdim MachineOperand &DstOp = MI.getOperand(DstIdx); 86284677Sdim MachineInstr *Mov = TII->buildMovInstr(&MBB, I, 87284677Sdim DstOp.getReg(), AMDGPU::OQAP); 88284677Sdim DstOp.setReg(AMDGPU::OQAP); 89284677Sdim int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), 90284677Sdim AMDGPU::OpName::pred_sel); 91284677Sdim int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), 92284677Sdim AMDGPU::OpName::pred_sel); 93284677Sdim // Copy the pred_sel bit 94284677Sdim Mov->getOperand(MovPredSelIdx).setReg( 95284677Sdim MI.getOperand(LDSPredSelIdx).getReg()); 96284677Sdim } 97284677Sdim 98284677Sdim switch (MI.getOpcode()) { 99284677Sdim default: break; 100284677Sdim // Expand PRED_X to one of the PRED_SET instructions. 101284677Sdim case AMDGPU::PRED_X: { 102284677Sdim uint64_t Flags = MI.getOperand(3).getImm(); 103284677Sdim // The native opcode used by PRED_X is stored as an immediate in the 104284677Sdim // third operand. 105284677Sdim MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I, 106284677Sdim MI.getOperand(2).getImm(), // opcode 107284677Sdim MI.getOperand(0).getReg(), // dst 108284677Sdim MI.getOperand(1).getReg(), // src0 109284677Sdim AMDGPU::ZERO); // src1 110284677Sdim TII->addFlag(PredSet, 0, MO_FLAG_MASK); 111284677Sdim if (Flags & MO_FLAG_PUSH) { 112284677Sdim TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1); 113284677Sdim } else { 114284677Sdim TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1); 115284677Sdim } 116284677Sdim MI.eraseFromParent(); 117284677Sdim continue; 118284677Sdim } 119284677Sdim 120284677Sdim case AMDGPU::INTERP_PAIR_XY: { 121284677Sdim MachineInstr *BMI; 122284677Sdim unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( 123284677Sdim MI.getOperand(2).getImm()); 124284677Sdim 125284677Sdim for (unsigned Chan = 0; Chan < 4; ++Chan) { 126284677Sdim unsigned DstReg; 127284677Sdim 128284677Sdim if (Chan < 2) 129284677Sdim DstReg = MI.getOperand(Chan).getReg(); 130284677Sdim else 131284677Sdim DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; 132284677Sdim 133284677Sdim BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY, 134284677Sdim DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 135284677Sdim 136284677Sdim if (Chan > 0) { 137284677Sdim BMI->bundleWithPred(); 138284677Sdim } 139284677Sdim if (Chan >= 2) 140284677Sdim TII->addFlag(BMI, 0, MO_FLAG_MASK); 141284677Sdim if (Chan != 3) 142284677Sdim TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST); 143284677Sdim } 144284677Sdim 145284677Sdim MI.eraseFromParent(); 146284677Sdim continue; 147284677Sdim } 148284677Sdim 149284677Sdim case AMDGPU::INTERP_PAIR_ZW: { 150284677Sdim MachineInstr *BMI; 151284677Sdim unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( 152284677Sdim MI.getOperand(2).getImm()); 153284677Sdim 154284677Sdim for (unsigned Chan = 0; Chan < 4; ++Chan) { 155284677Sdim unsigned DstReg; 156284677Sdim 157284677Sdim if (Chan < 2) 158284677Sdim DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; 159284677Sdim else 160284677Sdim DstReg = MI.getOperand(Chan-2).getReg(); 161284677Sdim 162284677Sdim BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW, 163284677Sdim DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 164284677Sdim 165284677Sdim if (Chan > 0) { 166284677Sdim BMI->bundleWithPred(); 167284677Sdim } 168284677Sdim if (Chan < 2) 169284677Sdim TII->addFlag(BMI, 0, MO_FLAG_MASK); 170284677Sdim if (Chan != 3) 171284677Sdim TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST); 172284677Sdim } 173284677Sdim 174284677Sdim MI.eraseFromParent(); 175284677Sdim continue; 176284677Sdim } 177284677Sdim 178284677Sdim case AMDGPU::INTERP_VEC_LOAD: { 179284677Sdim const R600RegisterInfo &TRI = TII->getRegisterInfo(); 180284677Sdim MachineInstr *BMI; 181284677Sdim unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( 182284677Sdim MI.getOperand(1).getImm()); 183284677Sdim unsigned DstReg = MI.getOperand(0).getReg(); 184284677Sdim 185284677Sdim for (unsigned Chan = 0; Chan < 4; ++Chan) { 186284677Sdim BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0, 187284677Sdim TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); 188284677Sdim if (Chan > 0) { 189284677Sdim BMI->bundleWithPred(); 190284677Sdim } 191284677Sdim if (Chan != 3) 192284677Sdim TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST); 193284677Sdim } 194284677Sdim 195284677Sdim MI.eraseFromParent(); 196284677Sdim continue; 197284677Sdim } 198284677Sdim case AMDGPU::DOT_4: { 199284677Sdim 200284677Sdim const R600RegisterInfo &TRI = TII->getRegisterInfo(); 201284677Sdim 202284677Sdim unsigned DstReg = MI.getOperand(0).getReg(); 203284677Sdim unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 204284677Sdim 205284677Sdim for (unsigned Chan = 0; Chan < 4; ++Chan) { 206284677Sdim bool Mask = (Chan != TRI.getHWRegChan(DstReg)); 207284677Sdim unsigned SubDstReg = 208284677Sdim AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 209284677Sdim MachineInstr *BMI = 210284677Sdim TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg); 211284677Sdim if (Chan > 0) { 212284677Sdim BMI->bundleWithPred(); 213284677Sdim } 214284677Sdim if (Mask) { 215284677Sdim TII->addFlag(BMI, 0, MO_FLAG_MASK); 216284677Sdim } 217284677Sdim if (Chan != 3) 218284677Sdim TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST); 219284677Sdim unsigned Opcode = BMI->getOpcode(); 220284677Sdim // While not strictly necessary from hw point of view, we force 221284677Sdim // all src operands of a dot4 inst to belong to the same slot. 222284677Sdim unsigned Src0 = BMI->getOperand( 223284677Sdim TII->getOperandIdx(Opcode, AMDGPU::OpName::src0)) 224284677Sdim .getReg(); 225284677Sdim unsigned Src1 = BMI->getOperand( 226284677Sdim TII->getOperandIdx(Opcode, AMDGPU::OpName::src1)) 227284677Sdim .getReg(); 228284677Sdim (void) Src0; 229284677Sdim (void) Src1; 230284677Sdim if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && 231284677Sdim (TRI.getEncodingValue(Src1) & 0xff) < 127) 232284677Sdim assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); 233284677Sdim } 234284677Sdim MI.eraseFromParent(); 235284677Sdim continue; 236284677Sdim } 237284677Sdim } 238284677Sdim 239284677Sdim bool IsReduction = TII->isReductionOp(MI.getOpcode()); 240284677Sdim bool IsVector = TII->isVector(MI); 241284677Sdim bool IsCube = TII->isCubeOp(MI.getOpcode()); 242284677Sdim if (!IsReduction && !IsVector && !IsCube) { 243284677Sdim continue; 244284677Sdim } 245284677Sdim 246284677Sdim // Expand the instruction 247284677Sdim // 248284677Sdim // Reduction instructions: 249284677Sdim // T0_X = DP4 T1_XYZW, T2_XYZW 250284677Sdim // becomes: 251284677Sdim // TO_X = DP4 T1_X, T2_X 252284677Sdim // TO_Y (write masked) = DP4 T1_Y, T2_Y 253284677Sdim // TO_Z (write masked) = DP4 T1_Z, T2_Z 254284677Sdim // TO_W (write masked) = DP4 T1_W, T2_W 255284677Sdim // 256284677Sdim // Vector instructions: 257284677Sdim // T0_X = MULLO_INT T1_X, T2_X 258284677Sdim // becomes: 259284677Sdim // T0_X = MULLO_INT T1_X, T2_X 260284677Sdim // T0_Y (write masked) = MULLO_INT T1_X, T2_X 261284677Sdim // T0_Z (write masked) = MULLO_INT T1_X, T2_X 262284677Sdim // T0_W (write masked) = MULLO_INT T1_X, T2_X 263284677Sdim // 264284677Sdim // Cube instructions: 265284677Sdim // T0_XYZW = CUBE T1_XYZW 266284677Sdim // becomes: 267284677Sdim // TO_X = CUBE T1_Z, T1_Y 268284677Sdim // T0_Y = CUBE T1_Z, T1_X 269284677Sdim // T0_Z = CUBE T1_X, T1_Z 270284677Sdim // T0_W = CUBE T1_Y, T1_Z 271284677Sdim for (unsigned Chan = 0; Chan < 4; Chan++) { 272284677Sdim unsigned DstReg = MI.getOperand( 273284677Sdim TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg(); 274284677Sdim unsigned Src0 = MI.getOperand( 275284677Sdim TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg(); 276284677Sdim unsigned Src1 = 0; 277284677Sdim 278284677Sdim // Determine the correct source registers 279284677Sdim if (!IsCube) { 280284677Sdim int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1); 281284677Sdim if (Src1Idx != -1) { 282284677Sdim Src1 = MI.getOperand(Src1Idx).getReg(); 283284677Sdim } 284284677Sdim } 285284677Sdim if (IsReduction) { 286284677Sdim unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 287284677Sdim Src0 = TRI.getSubReg(Src0, SubRegIndex); 288284677Sdim Src1 = TRI.getSubReg(Src1, SubRegIndex); 289284677Sdim } else if (IsCube) { 290284677Sdim static const int CubeSrcSwz[] = {2, 2, 0, 1}; 291284677Sdim unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); 292284677Sdim unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); 293284677Sdim Src1 = TRI.getSubReg(Src0, SubRegIndex1); 294284677Sdim Src0 = TRI.getSubReg(Src0, SubRegIndex0); 295284677Sdim } 296284677Sdim 297284677Sdim // Determine the correct destination registers; 298284677Sdim bool Mask = false; 299284677Sdim bool NotLast = true; 300284677Sdim if (IsCube) { 301284677Sdim unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 302284677Sdim DstReg = TRI.getSubReg(DstReg, SubRegIndex); 303284677Sdim } else { 304284677Sdim // Mask the write if the original instruction does not write to 305284677Sdim // the current Channel. 306284677Sdim Mask = (Chan != TRI.getHWRegChan(DstReg)); 307284677Sdim unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 308284677Sdim DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 309284677Sdim } 310284677Sdim 311284677Sdim // Set the IsLast bit 312284677Sdim NotLast = (Chan != 3 ); 313284677Sdim 314284677Sdim // Add the new instruction 315284677Sdim unsigned Opcode = MI.getOpcode(); 316284677Sdim switch (Opcode) { 317284677Sdim case AMDGPU::CUBE_r600_pseudo: 318284677Sdim Opcode = AMDGPU::CUBE_r600_real; 319284677Sdim break; 320284677Sdim case AMDGPU::CUBE_eg_pseudo: 321284677Sdim Opcode = AMDGPU::CUBE_eg_real; 322284677Sdim break; 323284677Sdim default: 324284677Sdim break; 325284677Sdim } 326284677Sdim 327284677Sdim MachineInstr *NewMI = 328284677Sdim TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); 329284677Sdim 330284677Sdim if (Chan != 0) 331284677Sdim NewMI->bundleWithPred(); 332284677Sdim if (Mask) { 333284677Sdim TII->addFlag(NewMI, 0, MO_FLAG_MASK); 334284677Sdim } 335284677Sdim if (NotLast) { 336284677Sdim TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST); 337284677Sdim } 338284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp); 339284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal); 340284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs); 341284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs); 342284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg); 343284677Sdim SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg); 344284677Sdim } 345284677Sdim MI.eraseFromParent(); 346284677Sdim } 347284677Sdim } 348284677Sdim return false; 349284677Sdim} 350