Searched refs:x3 (Results 1 - 25 of 1182) sorted by relevance

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/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx6_ccmreg.h40 #define SSI_CLK_SEL_M 0x3
77 #define CCGR0_AIPS_TZ1 (0x3 << 0)
78 #define CCGR0_AIPS_TZ2 (0x3 << 2)
79 #define CCGR0_ABPHDMA (0x3 << 4)
81 #define CCGR1_ECSPI1 (0x3 << 0)
82 #define CCGR1_ECSPI2 (0x3 << 2)
83 #define CCGR1_ECSPI3 (0x3 << 4)
84 #define CCGR1_ECSPI4 (0x3 << 6)
85 #define CCGR1_ECSPI5 (0x3 << 8)
86 #define CCGR1_ENET (0x3 << 1
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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dpopcountti2.c21 tu_int x3 = (tu_int)a; local
22 x3 = x3 - ((x3 >> 1) &
25 x3 = ((x3 >> 2) &
27 (x3 & (((tu_int)0x3333333333333333uLL << 64) | 0x3333333333333333uLL));
29 x3 = (x3 + (x3 >>
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/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dni_reg.h33 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
38 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
47 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
51 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
64 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
68 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
69 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
70 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)
73 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)
78 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) <<
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H A Dsi_reg.h37 # define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
41 # define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
46 # define SI_GRPH_Z(x) (((x) & 0x3) << 4)
47 # define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
71 # define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
84 # define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
/freebsd-11-stable/contrib/binutils/opcodes/
H A Dia64-asmtab.c2332 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2333 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2334 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2336 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2340 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2341 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2342 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2343 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2344 { 0x2, 0x3, 11, -1, -1, 37, 1, 5 },
2346 { 0x2, 0x3, 1
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/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Decore_hsi_fcoe.h192 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
280 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
282 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
284 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
286 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
289 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
291 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
293 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
295 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
298 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf
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H A Decore_hsi_iscsi.h109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
127 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 /* cf
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H A Decore_hsi_rdma.h63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
67 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
124 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
188 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
195 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_al
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H A Decore_hsi_roce.h140 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
191 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
384 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
532 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
534 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
536 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
571 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
573 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
575 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0c
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H A Decore_hsi_eth.h101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf
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H A Decore_hsi_iwarp.h110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
114 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
116 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf
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/freebsd-11-stable/lib/libc/powerpc/gen/
H A Dfpgetround.c46 return ((fp_rnd_t)(fpscr & 0x3));
/freebsd-11-stable/lib/libc/powerpc64/gen/
H A Dfpgetround.c46 return ((fp_rnd_t)(fpscr & 0x3));
/freebsd-11-stable/crypto/openssl/crypto/rc2/
H A Drc2_cbc.c141 register RC2_INT x0, x1, x2, x3, t; local
149 x3 = (RC2_INT) (l >> 16L);
156 t = (x0 + (x1 & ~x3) + (x2 & x3) + *(p0++)) & 0xffff;
158 t = (x1 + (x2 & ~x0) + (x3 & x0) + *(p0++)) & 0xffff;
160 t = (x2 + (x3 & ~x1) + (x0 & x1) + *(p0++)) & 0xffff;
162 t = (x3 + (x0 & ~x2) + (x1 & x2) + *(p0++)) & 0xffff;
163 x3 = (t << 5) | (t >> 11);
170 x0 += p1[x3 & 0x3f];
173 x3
187 register RC2_INT x0, x1, x2, x3, t; local
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/freebsd-11-stable/sys/mips/rmi/dev/xlr/
H A Dxgmac_mdio.h57 _mmio[0x11] = ((st_field & 0x3) << 30) |
58 ((op_type & 0x3) << 28) |
61 ((ta_field & 0x3) << 16) |
80 uint32_t op_type = 0x3; /* read operation */
85 _mmio[0x11] = ((st_field & 0x3) << 30) |
86 ((op_type & 0x3) << 28) |
89 ((ta_field & 0x3) << 16) |
113 _mmio[0x11] = ((st_field & 0x3) << 30) |
114 ((op_type & 0x3) << 28) |
117 ((ta_field & 0x3) << 1
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/freebsd-11-stable/sys/arm64/arm64/
H A Dcpufunc_asm.S50 * in x1. It will corrupt x0, x1, x2, and x3.
54 ldr x3, =dcache_line_size /* Load the D cache line size */
56 ldr x3, =idcache_line_size /* Load the I & D cache line size */
58 ldr x3, [x3]
59 sub x4, x3, #1 /* Get the address mask */
70 add x0, x0, x3 /* Move to the next line */
71 subs x1, x1, x3 /* Reduce the size */
/freebsd-11-stable/sys/mips/atheros/
H A Dar933x_uart.h49 #define AR933X_UART_CS_PARITY_M 0x3
54 #define AR933X_UART_CS_IF_MODE_M 0x3
59 #define AR933X_UART_CS_FLOW_CTRL_M 0x3
/freebsd-11-stable/usr.sbin/dumpcis/
H A Dcis.h167 #define CIS_FEAT_POWER(x) ((x) & 0x3)
171 #define CIS_FEAT_MEMORY(x) (((x) >> 5) & 0x3)
196 #define CIS_WAIT_SCALE(x) ((x) & 0x3)
262 #define CIS_MEM_LENSZ(x) (((x) >> 3) & 0x3)
263 #define CIS_MEM_ADDRSZ(x) (((x) >> 5) & 0x3)
279 #define CIS_MISC_DMA_REQ(x) (((x) >> 2) & 0x3)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInfo.h28 P = 0x3,
49 BRGE = 0x3,
/freebsd-11-stable/crypto/heimdal/lib/wind/
H A Dbidi_table.c18 {0x66d, 0x3},
65 {0x388, 0x3},
93 {0x9be, 0x3},
98 {0x9df, 0x3},
108 {0xa3e, 0x3},
112 {0xa72, 0x3},
116 {0xa8f, 0x3},
140 {0xb5f, 0x3},
144 {0xb8e, 0x3},
150 {0xba8, 0x3},
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/freebsd-11-stable/lib/libc/aarch64/gen/
H A Dsigsetjmp.S44 ldr x3, [x0]
47 cmp x2, x3
/freebsd-11-stable/lib/libc/i386/sys/
H A Di386_clr_watch.c42 DBREG_DRX(d,7) = DBREG_DRX(d,7) & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
/freebsd-11-stable/sys/dev/isci/scil/
H A Dintel_sat.h89 #define SAT_PROTOCOL_PACKET_PIO_DATA_IN (SAT_PROTOCOL_PACKET | 0x3)
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/
H A Darm64intr.h29 _ARM64_BARRIER_OSH = 0x3,
H A Darmintr.h26 _ARM_BARRIER_OSH = 0x3,

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