Searched refs:v2i64 (Results 1 - 25 of 30) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp210 // v2i64/v4i64 mul is custom lowered as a series of long:
215 { ISD::MUL, MVT::v2i64, 17 },
217 { ISD::ADD, MVT::v2i64, 4 },
218 { ISD::SUB, MVT::v2i64, 4 },
304 { ISD::SRA, MVT::v2i64, 1 },
468 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
487 { ISD::MUL, MVT::v2i64, 1 },
532 { ISD::SRA, MVT::v2i64, 1 },
565 { ISD::SHL, MVT::v2i64,
[all...]
H A DX86ISelLowering.cpp873 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
890 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
902 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
919 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
920 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
926 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
947 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
952 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
959 // Custom lower v2i64 and v2f64 selects.
961 setOperationAction(ISD::SELECT, MVT::v2i64, Custo
[all...]
H A DX86ISelDAGToDAG.cpp4027 case MVT::v2i64:
4053 case MVT::v2i64:
4074 case MVT::v2i64:
4104 case MVT::v2i64:
4130 case MVT::v2i64:
4151 case MVT::v2i64:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp328 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
331 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
336 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
339 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
369 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
372 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
374 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
375 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
378 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
968 { TTI::SK_Broadcast, MVT::v2i64,
[all...]
H A DAArch64ISelDAGToDAG.cpp645 case MVT::v2i64:
656 case MVT::v2i64:
3203 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3230 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3257 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3284 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3311 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3338 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3365 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3392 } else if (VT == MVT::v2i64 || V
[all...]
H A DAArch64SelectionDAGInfo.cpp101 MVT::v2i64,
H A DAArch64ISelLowering.cpp162 addQRTypeForNEON(MVT::v2i64);
749 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
750 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
771 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
774 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
778 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
781 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
927 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
1193 // Disregard v2i64. Memcpy lowering produces those and splitting
1195 VT == MVT::v2i64;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp221 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
222 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
369 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
370 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },
373 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
374 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
375 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 8 },
376 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 2 },
583 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
605 {ISD::VECTOR_SHUFFLE, MVT::v2i64,
[all...]
H A DARMISelLowering.cpp215 VT != MVT::v2i64 && VT != MVT::v1i64)
364 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
372 // We can do bitwise operations on v2i64 vectors
373 setOperationAction(ISD::AND, MVT::v2i64, Legal);
374 setOperationAction(ISD::OR, MVT::v2i64, Legal);
375 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
769 addQRTypeForNEON(MVT::v2i64);
849 // Neon does not support some operations on v1i64 and v2i64 types.
854 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
884 setOperationAction(ISD::CTPOP, MVT::v2i64, Custo
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp146 case MVT::v2i64:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h108 v2i64 = 58, // 2 x i64
352 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
496 case v2i64:
640 case v2i64:
762 case v2i64:
975 if (NumElements == 2) return MVT::v2i64;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
122 setOperationAction(Op, MVT::v2i64, Expand);
136 for (auto T : {MVT::v2i64, MVT::v2f64})
143 for (auto T: {MVT::v2i64, MVT::v2f64})
151 setOperationAction(Op, MVT::v2i64, Custom);
159 for (auto T : {MVT::v2i64, MVT::v2f64})
164 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
171 for (auto T : {MVT::v2i64, MVT::v2f64})
181 setOperationAction(Op, MVT::v2i64, Expand);
203 setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custo member in class:MVT
[all...]
H A DWebAssemblyFastISel.cpp143 case MVT::v2i64:
693 case MVT::v2i64:
807 case MVT::v2i64:
1328 case MVT::v2i64:
H A DWebAssemblyAsmPrinter.cpp61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp1016 ViaVecTy = MVT::v2i64;
1108 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1198 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1245 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
H A DMipsSEISelLowering.cpp121 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
1381 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1387 if (ResVecTy == MVT::v2i64) {
1435 if (VecTy == MVT::v2i64) {
1436 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1473 if (VecTy == MVT::v2i64) {
1485 ISD::BITCAST, DL, MVT::v2i64,
1496 if (VecTy == MVT::v2i64)
1513 MVT ResEltTy = ResTy == MVT::v2i64
[all...]
H A DMipsSEInstrInfo.cpp280 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
358 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp594 // For v2i64, these are only valid with P8Vector. This is corrected after
699 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
700 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
701 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
702 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
705 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
736 // Without hasP8Altivec set, v2i64 SMAX isn't available.
739 setOperationAction(ISD::ABS, MVT::v2i64, Expand);
747 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
795 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Lega
[all...]
H A DPPCTargetTransformInfo.cpp864 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
H A DPPCISelDAGToDAG.cpp3924 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
4003 else if (VecVT == MVT::v2i64)
4013 else if (VecVT == MVT::v2i64)
4023 else if (VecVT == MVT::v2i64)
4980 N->getValueType(0) == MVT::v2i64)
4992 N->getValueType(0) == MVT::v2i64)) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp107 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
357 if (VT != MVT::v2i64)
399 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
401 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
408 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
410 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
412 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
414 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Lega
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/
H A Dmsa.h26 typedef long long v2i64 __attribute__((vector_size(16), aligned(16))); typedef
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp203 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp97 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
98 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
197 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
198 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
211 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
212 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
213 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
214 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp123 case MVT::v2i64: return "MVT::v2i64";

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