Searched refs:rd32 (Results 1 - 14 of 14) sorted by relevance

/freebsd-11-stable/sys/dev/ixl/
H A Dixl_pf_i2c.c78 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
115 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
166 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
175 i2cctl = rd32(hw, IXL_I2C_REG(hw));
180 i2cctl = rd32(hw, IXL_I2C_REG(hw));
203 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
212 i2cctl = rd32(hw, IXL_I2C_REG(hw));
220 i2cctl = rd32(hw, IXL_I2C_REG(hw));
253 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
303 i2cctl = rd32(h
[all...]
H A Di40e_adminq.c319 reg = rd32(hw, hw->aq.asq.bal);
355 reg = rd32(hw, hw->aq.arq.bal);
753 while (rd32(hw, hw->aq.asq.head) != ntc) {
755 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
790 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
830 val = rd32(hw, hw->aq.asq.head);
987 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
1058 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1060 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
H A Di40e_lan_hmc.c136 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
139 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
156 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
162 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
179 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);
185 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
202 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);
208 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
H A Dif_ixlv.c1573 reg = rd32(hw, I40E_VFGEN_RSTAT) &
1996 reg = rd32(hw, I40E_VFINT_ICR01);
1997 mask = rd32(hw, I40E_VFINT_ICR0_ENA1);
1999 reg = rd32(hw, I40E_VFINT_DYN_CTL01);
2037 rd32(hw, I40E_VFGEN_RSTAT);
2049 rd32(hw, I40E_VFGEN_RSTAT);
2069 rd32(hw, I40E_VFGEN_RSTAT);
2588 val = rd32(hw, I40E_VFGEN_RSTAT) &
2774 hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) |
2775 ((u64)rd32(h
[all...]
H A Di40e_nvm.c59 gens = rd32(hw, I40E_GLNVM_GENS);
66 fla = rd32(hw, I40E_GLNVM_FLA);
103 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
118 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
186 srctl = rd32(hw, I40E_GLNVM_SRCTL);
233 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
1258 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
H A Di40e_common.c397 return !!(rd32(hw, hw->aq.asq.len) &
400 return !!(rd32(hw, hw->aq.asq.len) &
1012 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1015 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1017 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1168 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1309 reg = rd32(hw, I40E_GLGEN_RSTAT);
1340 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347 reg = rd32(hw, I40E_GLGEN_RSTAT);
1359 reg = rd32(h
[all...]
H A Di40e_osdep.h227 #define rd32(a, reg) rd32_osdep((a)->back, (reg)) macro
H A Dixl_pf_main.c172 return (rd32(&pf->hw, I40E_GL_FWSTS) & I40E_GL_FWSTS_FWS1B_MASK);
729 icr0 = rd32(hw, I40E_PFINT_ICR0);
825 reg = rd32(hw, I40E_PFINT_ICR0);
826 mask = rd32(hw, I40E_PFINT_ICR0_ENA);
841 rstat_reg = rd32(hw, I40E_GLGEN_RSTAT);
870 reg = rd32(hw, I40E_PFHMC_ERRORINFO);
874 reg = rd32(hw, I40E_PFHMC_ERRORDATA);
1575 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3402 reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
3408 reg = rd32(h
[all...]
H A Dixl_pf_iov.c356 ciad = rd32(hw, I40E_PF_PCI_CIAD);
373 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num));
399 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num));
409 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num));
1648 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index));
1657 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA);
H A Dixl_txrx.c2238 val = rd32(que->vsi->hw, que->txr.tail);
2260 val = rd32(que->vsi->hw, que->rxr.tail);
H A Di40e_dcb.c53 reg = rd32(hw, I40E_PRTDCB_GENS);
/freebsd-11-stable/sys/mips/malta/
H A Dgt_pci_bus_space.c219 #define rd32(a) le32toh(readl(a)) macro
239 return (rd32(handle + offset));
259 *addr++ = rd32(baddr);
286 *addr++ = rd32(baddr);
/freebsd-11-stable/sys/mips/cavium/
H A Doctopci_bus_space.c199 #define rd32(a) le32toh(cvmx_read64_uint32(a)) macro
256 return (rd32(handle + offset));
286 *addr++ = rd32(baddr);
326 *addr++ = rd32(baddr);
556 wr32(addr2, rd32(addr1));
561 wr32(addr2, rd32(addr1));
/freebsd-11-stable/sys/mips/mips/
H A Dbus_space_generic.c197 #define rd32(a) cvmx_read64_uint32(a) macro
207 #define rd32(a) sb_big_endian_read32(a) macro
214 #define rd32(a) readl(a) macro
295 return (rd32(handle + offset));
335 *addr++ = rd32(baddr);
388 *addr++ = rd32(baddr);
704 wr32(addr2, rd32(addr1));
709 wr32(addr2, rd32(addr1));

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