| /freebsd-11-stable/sys/dev/drm2/radeon/ |
| H A D | radeon_display.c | 750 u32 post_div,
755 u32 tmp = post_div * ref_div;
770 u32 vco, post_div, tmp; local
773 return pll->post_div;
787 post_div = vco / target_clock;
792 post_div++;
795 post_div--;
798 if (post_div > pll->max_post_div)
799 post_div = pll->max_post_div;
800 else if (post_div < pl
748 avivo_get_fb_div(struct radeon_pll *pll, u32 target_clock, u32 post_div, u32 ref_div, u32 *fb_div, u32 *frac_fb_div) argument
817 u32 post_div = avivo_get_post_div(pll, target_clock); local
898 uint32_t post_div; local
[all...] |
| H A D | radeon_clocks.c | 43 uint32_t fb_div, ref_div, post_div, sclk; local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
59 if (post_div == 2)
61 else if (post_div == 3)
63 else if (post_div == 4)
73 uint32_t fb_div, ref_div, post_div, mclk; local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
89 if (post_div == 2)
91 else if (post_div == 3)
93 else if (post_div
351 calc_eng_mem_clock(struct radeon_device *rdev, uint32_t req_clock, int *fb_div, int *post_div) argument
394 int fb_div, post_div; local
[all...] |
| H A D | radeon_legacy_tv.c | 872 int post_div; local
874 case 1: post_div = 0; break;
875 case 2: post_div = 1; break;
876 case 3: post_div = 4; break;
877 case 4: post_div = 2; break;
878 case 6: post_div = 6; break;
879 case 8: post_div = 3; break;
880 case 12: post_div = 7; break;
882 default: post_div = 5; break;
884 return post_div;
[all...] |
| H A D | radeon_legacy_crtc.c | 732 } *post_div, post_divs[] = { local
798 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
799 if (post_div->divider == post_divider)
803 if (!post_div->divider)
804 post_div = &post_divs[0];
819 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
|
| H A D | atombios_crtc.c | 778 u32 post_div,
805 args.v1.ucPostDiv = post_div;
815 args.v2.ucPostDiv = post_div;
825 args.v3.ucPostDiv = post_div;
842 args.v5.ucPostDiv = post_div;
864 args.v6.ucPostDiv = post_div;
1000 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1021 pll->post_div = radeon_crtc->pll_post_div;
1026 &fb_div, &frac_fb_div, &ref_div, &post_div);
1029 &fb_div, &frac_fb_div, &ref_div, &post_div);
769 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
[all...] |
| H A D | radeon_mode.h | 160 uint32_t post_div; member in struct:radeon_pll
|
| /freebsd-11-stable/sys/arm/allwinner/clk/ |
| H A D | aw_cpusclk.c | 130 uint32_t val, src_sel, post_div, clk_ratio; local
142 post_div = ((val & A80_CPUS_POST_DIV) >>
147 *freq = *freq / post_div / clk_ratio;
154 post_div = ((val & A83T_CPUS_POST_DIV) >>
159 *freq = *freq / post_div / clk_ratio;
|
| H A D | aw_pll.c | 220 uint32_t val, post_div, n, pre_div; local
226 post_div = (val & A10_PLL2_POST_DIV) >> A10_PLL2_POST_DIV_SHIFT;
227 if (post_div == 0)
228 post_div = 1;
238 *freq = (*freq * 2 * n) / pre_div / post_div / 2;
260 uint32_t val, post_div, n, pre_div; local
268 * PLL2-1X output frequency is (48MHz * n) / pre_div / post_div / 2.
277 post_div = 4;
278 n = (*fout * pre_div * post_div * 2) / (2 * fin);
283 val |= (post_div << A10_PLL2_POST_DIV_SHIF
477 uint32_t val, post_div, n, pre_div; local
517 uint32_t val, post_div, n, pre_div; local
[all...] |