Searched refs:nae_base (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/sys/mips/nlm/hal/
H A Ducore_loader.h43 nlm_ucore_load_image(uint64_t nae_base, int ucore) argument
45 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
60 nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data) argument
63 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
68 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
70 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
76 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
81 nlm_ucore_read_sharedmem(uint64_t nae_base, int index) argument
83 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
86 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CF
100 nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done) argument
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H A Dnae.h604 void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
611 void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
630 int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
634 void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);
/freebsd-11-stable/sys/mips/nlm/dev/net/
H A Dmdio.c45 nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block, argument
61 mdio_ld_cmd = nlm_read_nae_reg(nae_base,
64 nlm_write_nae_reg(nae_base,
69 nlm_write_nae_reg(nae_base,
74 nlm_write_nae_reg(nae_base,
79 while(nlm_read_nae_reg(nae_base,
84 nlm_write_nae_reg(nae_base,
89 return nlm_read_nae_reg(nae_base,
95 nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block, argument
111 mdio_ld_cmd = nlm_read_nae_reg(nae_base,
146 nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block, int intf_type) argument
178 nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx) argument
239 nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block, int intf_type, int phyaddr, int regidx, uint16_t val) argument
301 nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block, int intf_type) argument
326 nlm_mdio_reset_all(uint64_t nae_base) argument
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H A Dnae.c47 nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks) argument
53 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, fifo_mask);
55 data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP);
58 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, 0);
62 nlm_program_nae_parser_seq_fifo(uint64_t nae_base, int maxports, argument
73 nlm_write_nae_reg(nae_base, NAE_PARSER_SEQ_FIFO_CFG, val);
79 nlm_setup_rx_cal_cfg(uint64_t nae_base, int total_num_ports, argument
104 nlm_write_nae_reg(nae_base,
116 nlm_setup_tx_cal_cfg(uint64_t nae_base, int total_num_ports, argument
132 nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CAL_LEN_RE
152 nlm_deflate_frin_fifo_carving(uint64_t nae_base, int total_num_ports) argument
169 uint64_t nae_base; local
208 nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes, int num_contexts, int *poe_cl_tbl) argument
222 nlm_setup_vfbid_mapping(uint64_t nae_base) argument
238 nlm_setup_flow_crc_poly(uint64_t nae_base, uint32_t poly) argument
244 nlm_setup_iface_fifo_cfg(uint64_t nae_base, int maxports, struct nae_port_config *cfg) argument
264 nlm_setup_rx_base_config(uint64_t nae_base, int maxports, struct nae_port_config *cfg) argument
286 nlm_setup_rx_buf_config(uint64_t nae_base, int maxports, struct nae_port_config *cfg) argument
317 nlm_setup_freein_fifo_cfg(uint64_t nae_base, struct nae_port_config *cfg) argument
358 nlm_program_flow_cfg(uint64_t nae_base, int port, uint32_t cur_flow_base, uint32_t flow_mask) argument
369 xlp_ax_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl, int mode) argument
461 xlp_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl, int mode) argument
497 xlp_nae_config_lane_gmac(uint64_t nae_base, int cplx_mask) argument
569 config_egress_fifo_carvings(uint64_t nae_base, int hwport, int start_ctxt, int num_ctxts, int max_ctxts, struct nae_port_config *cfg) argument
693 config_egress_fifo_credits(uint64_t nae_base, int hwport, int start_ctxt, int num_ctxts, int max_ctxts, struct nae_port_config *cfg) argument
750 nlm_config_freein_fifo_uniq_cfg(uint64_t nae_base, int port, int nblock_free_desc) argument
763 nlm_config_ucore_iface_mask_cfg(uint64_t nae_base, int port, int nblock_ucore_mask) argument
774 nlm_nae_init_netior(uint64_t nae_base, int nblocks) argument
807 nlm_nae_init_ingress(uint64_t nae_base, uint32_t desc_size) argument
831 nlm_nae_init_egress(uint64_t nae_base) argument
859 nlm_nae_init_ucore(uint64_t nae_base, int if_num, u_int ucore_mask) argument
877 nlm_setup_l2type(uint64_t nae_base, int hwport, uint32_t l2extlen, uint32_t l2extoff, uint32_t extra_hdrsize, uint32_t proto_offset, uint32_t fixed_hdroff, uint32_t l2proto) argument
893 nlm_setup_l3ctable_mask(uint64_t nae_base, int hwport, uint32_t ptmask, uint32_t l3portmask) argument
905 nlm_setup_l3ctable_even(uint64_t nae_base, int entry, uint32_t l3hdroff, uint32_t ipcsum_en, uint32_t l4protooff, uint32_t l2proto, uint32_t eth_type) argument
920 nlm_setup_l3ctable_odd(uint64_t nae_base, int entry, uint32_t l3off0, uint32_t l3len0, uint32_t l3off1, uint32_t l3len1, uint32_t l3off2, uint32_t l3len2) argument
936 nlm_setup_l4ctable_even(uint64_t nae_base, int entry, uint32_t im, uint32_t l3cm, uint32_t l4pm, uint32_t port, uint32_t l3camaddr, uint32_t l4proto) argument
952 nlm_setup_l4ctable_odd(uint64_t nae_base, int entry, uint32_t l4off0, uint32_t l4len0, uint32_t l4off1, uint32_t l4len1) argument
965 nlm_enable_hardware_parser(uint64_t nae_base) argument
1191 nlm_enable_hardware_parser_per_port(uint64_t nae_base, int block, int port) argument
1204 nlm_prepad_enable(uint64_t nae_base, int size) argument
1215 nlm_setup_1588_timer(uint64_t nae_base, struct nae_port_config *cfg) argument
1261 nlm_mac_enable(uint64_t nae_base, int nblock, int port_type, int port) argument
1298 nlm_mac_disable(uint64_t nae_base, int nblock, int port_type, int port) argument
1338 nlm_nae_set_ior_credit(uint64_t nae_base, uint32_t ifmask, uint32_t valmask) argument
1356 nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type, int port, uint32_t desc_size) argument
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H A Dxaui.c45 nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask) argument
64 lane_enable = nlm_read_nae_reg(nae_base,
74 nlm_write_nae_reg(nae_base,
80 lane_enable = nlm_read_nae_reg(nae_base,
90 nlm_write_nae_reg(nae_base,
103 xlp_nae_lane_reset_txpll(nae_base,
106 xlp_ax_nae_lane_reset_txpll(nae_base, block,
122 regval = nlm_read_nae_reg(nae_base, reg);
127 regval = nlm_read_nae_reg(nae_base, reg);
132 regval = nlm_read_nae_reg(nae_base, re
186 nlm_config_xaui_mtu(uint64_t nae_base, int nblock, int max_tx_frame_sz, int max_rx_frame_sz) argument
198 nlm_config_xaui(uint64_t nae_base, int nblock, int max_tx_frame_sz, int max_rx_frame_sz, int vlan_pri_en) argument
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H A Dsgmii.c43 nlm_configure_sgmii_interface(uint64_t nae_base, int block, int port, argument
54 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
59 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2);
63 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
66 nlm_write_nae_reg(nae_base, SGMII_MAX_FRAME(block, port), mtu);
70 nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask) argument
72 xlp_nae_config_lane_gmac(nae_base, cplx_mask);
76 nlm_nae_setup_mac(uint64_t nae_base, int nblock, int iface, int reset, argument
81 mac_cfg1 = nlm_read_nae_reg(nae_base,
83 mac_cfg2 = nlm_read_nae_reg(nae_base,
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H A Dxlpge.c325 uint64_t nae_base = sc->base; local
330 nlm_config_xaui(nae_base, nblock, mtu,
332 nlm_config_freein_fifo_uniq_cfg(nae_base,
334 nlm_config_ucore_iface_mask_cfg(nae_base,
337 nlm_program_flow_cfg(nae_base, port, cur_flow_base, flow_mask);
340 nlm_configure_sgmii_interface(nae_base, nblock, port, mtu, 0);
344 nlm_nae_init_netior(nae_base, sc->nblocks);
345 nlm_nae_open_if(nae_base, nblock, sc->cmplx_type[nblock], port,
350 nlm_nae_init_ucore(nae_base, port, ucore_mask);
356 uint64_t nae_base; local
385 uint64_t nae_base; local
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