Searched refs:gtt (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/sys/dev/drm2/i915/
H A Di915_gem_gtt.c128 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
131 first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
152 if (dev_priv->mm.gtt->needs_dmar) {
178 ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
310 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
314 if (dev_priv->mm.gtt->needs_dmar)
363 if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
377 if (unlikely(dev_priv->mm.gtt->do_idle_maps))
388 gtt_pte_t __iomem *gtt_base = dev_priv->mm.gtt
[all...]
H A Di915_gem_stolen.c82 base -= dev_priv->mm.gtt->stolen_size;
176 unsigned long prealloc_size = dev_priv->mm.gtt->stolen_size;
183 dev_priv->mm.gtt->stolen_size, dev_priv->mm.stolen_base);
H A Di915_dma.c1419 ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1421 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1541 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1542 dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1738 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE,
1961 * manage the gtt, we need to claim that all intel devices are agp. For
H A Di915_drv.h761 /** Bridge to intel-gtt-ko */
762 struct intel_gtt *gtt; member in struct:drm_i915_private::__anon9876
767 /** List of all objects in gtt_space. Used to restore gtt
1040 * Is the object at the current location in the gtt mappable and
1046 * Whether the current gtt mapping needs to be mappable (and isn't just
H A Dintel_ringbuffer.c1194 dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, ring->size,
H A Di915_gem.c477 /* If we're not in the cpu read domain, set ourself into the gtt
813 /* If we're not in the cpu write domain, set ourself into the gtt
989 /* Note that the gtt paths might fail with non-page-backed user
990 * pointers (e.g. gtt mappings when moving data between
1989 * array, hence protect them from being reaped by removing them from gtt
2717 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
4304 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4305 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4309 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_ttm.c514 struct radeon_ttm_tt *gtt = (void*)ttm; local
517 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
522 r = radeon_gart_bind(gtt->rdev, gtt->offset,
523 ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
526 ttm->num_pages, (unsigned)gtt->offset);
534 struct radeon_ttm_tt *gtt = (void *)ttm; local
536 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
542 struct radeon_ttm_tt *gtt local
559 struct radeon_ttm_tt *gtt; local
586 struct radeon_ttm_tt *gtt = (void *)ttm; local
646 struct radeon_ttm_tt *gtt = (void *)ttm; local
[all...]
H A Drs400.c217 u32 *gtt = rdev->gart.ptr; local
227 gtt[i] = entry;
H A Dr100.c703 u32 *gtt = rdev->gart.ptr; local
708 gtt[i] = cpu_to_le32(lower_32_bits(addr));
/freebsd-11-stable/sys/dev/agp/
H A Dagp_i810.h42 /* Special gtt memory types */
56 /* Total number of gtt entries. */
58 /* Part of the gtt that is mappable by the cpu, for those chips where
59 * this is not the full gtt. */
69 uint32_t *gtt; member in struct:intel_gtt

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